Refereed Conference Publications

 

1. Moshovos, A., G. Memik, G. Mittal, A. Baniasadi and A. Choudhary, “JETTY: Reducing snoop-induced power consumption in small-scale, bus-based SMP systems”, Technical Report, CPDC, Northwestern University, 1999.

 

2. Baniasadi, A. and A. Moshovos, “Instruction distribution heuristics for quad-cluster dynamically-scheduled superscalar processors”, in Proc. 33rd ACM/IEEE International Symposium on Microarchitecture, MICRO-33, pp. 337-348, December 2000.

 

3. Moshovos, A., D.N. Pnevmatikatos, and A. Baniasadi, “Slice-Processor: An implementation of operation-based prediction”, in Proc. International Conference on Super Computing, ICS-'01, pp. 167-178, June, 2001.

 

4. Baniasadi, A. and A. Moshovos, “Instruction flow-based front-end throttling for power-aware high-performance processors”, in Proc. International Symposium on Low Power Electronics and Design, ISLPED-'01, pp. 16-22, August, 2001.

 

5. Baniasadi, A. and A. Moshovos, “Asymmetric-frequency clustering: A power-aware back-end for high-performance processors”, in Proc. International Symposium on Low Power Electronics and Design, ISLPED-'02, pp. 255-259, August, 2002.

 

6. Baniasadi, A. and A. Moshovos, “Branch predictor prediction: A power-aware branch predictor for high-performance processors”, in Proc. International Conference on Computer Design, ICCD-'02, pp. 458-462, September, 2002.

 

7. Baniasadi, A., “Back-end dynamic resource allocation heuristics for power-aware high-performance clustered architectures”, in Proc. Euro Micro Symposium on Digital System Design Architectures, Methods and Tools, DSD, 2003.

 

8. Baniasadi, A., “Power-aware branch predictor for high-performance processors”, in Proc. International Workshop on Power and Timing Modeling Optimization and Simulation, PATMOS, 2003.

 

9. Zarrabi, S., and A. Baniasadi, “Application-based performance analysis of clustered processors”, in Proc.Canadian Conference of Electrical and Computer Engineering, CCECE, 2004, pp. 959-964.

 

10. Baniasadi, A., and A. Moshovos, “SEPAS: A highly accurate and energy-efficient branch predictor”, in Proc. International Symposium on Low Power Electronics and Design, ISLPED, 2004, pp. 38-43.

 

11. Atoofian, E., A. Baniasadi, and N. Dimopoulos, “Improving performance by speculating trivializing operands in trivial instructions”, in Proc. of Second Value-Prediction and Value-Based Optimization Workshop (VPW2), held in conjunction with the Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-11), 2004.

 

12. Atoofian, E., and A. Baniasadi, “Improving energy-efficiency by bypassing trivial computations”, in Proc. of First Workshop on High-Performance, Power-Aware Computing, in conjunction with International Parallel and Distributed Processing Symposium (IPDPS'2005).

 

13. Baniasadi, A., “Balancing clustering-induced stalls in clustered processors to improve performance”, in Proc. of Computing Frontiers Conference, CF, 2005.

 

14.  Salamat, B. and Baniasadi, A., “Area-Aware Pipeline Gating for Embedded Processors”, in Proc. of the International Workshop on Power and Timing Modeling Optimization and Simulation, PATMOS, 2005.

 

15.  Ghoneima, M., Atoofian, E., Baniasadi, A. and Ismail, Y. “Low-Power Prediction    Based Data Transfer Architecture”, in Proc. of IEEE Custom Integrated Circuits Conference (CICC 2005)

 

16.  Homayoun, H. and Baniasadi, A., “Analysis of Functional Unit Power Gating in Embedded Processors”,in Proc. of the IFIP International Conference on VLSI (VLSI-SOC 2005)

 

17. Baniasadi, A. and Salamat, B., “Power-Aware Scoreboard for Multimedia Processors”, in Proc. of the7th Workshop on Media and Stream Processors (MSP-7) held in conjunction with the 38th International Symposium on Microarchitecture (MICRO 2005), pp. 7-11.

 

18. Jokar Deris, K. and Baniasadi, A., “Branchless Cycle Prediction for Embedded Processors”, in Proc. of the 21st ACM Symposium on Applied Computing SAC 2006,  pp. 928-932.

 

19. Jokar Deris, K. and Baniasadi, A., “SABA: a Zero Timing Overhead Power-Aware    BTB for High-Performance Processors”, in of the 2nd workshop on UNIQUE CHIPS and SYSTEMS (UCAS-2) held in conjunction with IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS06).

 

20.  Homayoun, H. and Baniasadi, A., “Using Lazy Instruction Prediction to Reduce Processor Wakeup Power Dissipation”, in of the 2nd workshop on UNIQUE CHIPS and SYSTEMS (UCAS-2) held in conjunction with IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS06).

 

21.  Homayoun, H. and Baniasadi, A., “Reducing Execution Unit Leakage Power in Embedded Processors”,in of the proceedings of the 6th SAMOS Workshop (SAMOS-2006), pp. 299-308.

 

22.  Baniasadi, A., Salamat, B. and Jokar Deris, K., “Area-Aware Performance and Power Optimizations for Resource Constrained Embedded Processors”, in the proceedings of the IC-SAMOS conference, (IC-SAMOS-2006).

 

23.  Atoofian, E., Baniasadi, A. and Khosrow-khavar, F., “Using Speculation Cost Predictability in Low-Power Cost-Aware Branch Prediction”, in the proceedings of the Workshop on Complexity-Effective Design held in conjunction with the 33rd International Symposium on Computer Architecture (ISCA-2006), pp. 54-59.

 

24.  Jokar Deris, K. and Baniasadi, A., “Investigating Cache Energy and Latency Break-even Points in High-Performance Processors”, in the MEDEA (MEmory performance: DEaling with Applications, systems and architecture) workshop held in conjunction with PACT 2006, pp. 13-20.

 

25.  Jokar Deris, K. and Baniasadi, A., “Investigating Cache Energy Efficiency in Multimedia Processors”, in the Proc. Canadian Conference on Electrical and Computer Engineering 2007.

 

26.  Atoofian, E., and A. Baniasadi, “A Power-Aware Prediction-Based Cache Coherence
Protocol for Chip Multiprocessors”, in Proc. of Third Workshop on High-Performance, Power-Aware Computing, in conjunction with International Parallel and Distributed Processing Symposium (IPDPS'2007), pp. 1-8.

 

27.  Aasaraai, K., Baniasadi, A., and Atoofian, E., “Computational and Storage Power Optimizations for the O-GEHL Branch Predictor”, in Proc. of Computing Frontiers Conference, CF, 2007, pp. 105-112.

 

28.  Atoofian, E., Baniasadi, A., and Aasaraai, K., “Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols”, in Proc. of Computing Frontiers Conference, CF, 2007, pp. 259-266.

 

29.  Aasaraai, K., and Baniasadi, A., “A Power-Aware Alternative for the Perceptron Branch Predictor”, in Proc. of The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), pp. 198-208.

 

30.  Vanderster, D., Baniasadi, A., and Dimopoulos, N., “Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters”, in Proc. of The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), pp. 175-185.

 

31.  Atoofian, E., Baniasadi, A., "Exploiting Program Cyclic Behavior to Reduce Memory Latency in Embedded Processors", in Proc. of the 23rd ACM Symposium on Applied Computing SAC 2008.

 

32.  Jokar Deris, K., Baniasadi, A., "Analysis of Non-Optimal LRU Decisions in High-performance Processors", in Proc. of the 20th IEEE technically co-sponsored International Conference on Microelectronics ICM 2008.

 

33.   Eslami, F., Baniasadi, A., Farahani, M., “Application Specific Transistor Sizing for Low Power Full Adders”, in Proc. of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors,    June 2009,  pp.,195-198.

 

34.   Ardalan, N., and Baniasadi, A., “Write Invalidation Analysis in Chip Multiprocessors”, in Proc. of the Nineteenth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 2009.

 

35.   Jooya, A., Baniasaadi, A., and Analoui, M., “History-Aware, Resource-Based Dynamic Scheduling for Heterogeneous Multi-core Processors” in proc. of the 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects In conjunction with the 36th International Symposium on Computer Architecture (ISCA-36), June 2009.

 

36.   Baniasadi, A., and Jokar Deris, K., “Reducing Non-Optimal LRU Decision Frequency in Chip Multiprocessors” in proc. of the  IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, August 2009.

 

37.   Farahani, M., and Baniasadi, A., “Temperature Reduction Analysis in Sentry Tag Cache Systems”, in the proc. of  MEDEA 2009 Workshop MEmory performance: DEaling with Applications, systems and architecture held in conjunction with PACT 2009 Conference Sept. 12-16 2009.

 

38.  Hajkazemi, M., Haghdoost, A., Baniasadi, A., “Reconfiguring the Carry Look-Ahead Adder Using Application Behavior in Embedded Processors”, in proc. of ECTI-CON May 2010.

 

39.  Salehi, M., and Baniasadi, A, “Storage-Aware Value Prediction” in proc. of the13th EuromicroConference on Digital System Design (DSD).  September 2010.

 

40.   Shafie, A., Shahidi, N., and Baniasadi, A., “Using Partial Tag Comparison in Low-Power Snoop-based Chip Multiprocessors”, in proc. of the 2nd Workshop on Energy Efficient Design (WEED 2010) in conjunction with the 37th International Symposium on Computer Architecture (ISCA-37), June 2010.

 

41.  Haghdoost, A., Asadi, H., and Baniasadi, A., “Using Input-to-Output Masking for System-Level Vulnerability Estimation in High-Performance Processors”, in proc. of the 15th CSI Symposium on Computer Architecture & Digital Systems (CADS-37), September 2010.

 

42.  Haghdoost, A., Asadi, H., and Baniasadi, A., “System-Level Vulnerability Estimation for Cache Memories”, in proc. of the 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'10) December 2010.

 

43.  Shafie, A., Shahidi, N., and Baniasadi, A., “HELIA: Heterogeneous Interconnect for Low Resolution Cache Access in Snoop-based Chip Multiprocessors”, in proc. of the 28thInternational Conference on Computer Design (ICCD 2010), October 2010.

 

44.  Faraji, I., Baniasadi, A., “Time-based Snoop Filtering in Chip Multiprocessors”, in proc. Workshop on Energy-Efficient Design at International Symposium on Computer Architecture (ISCA-38), June 2011.

 

45.  Lashgar, A., Baniasadi, A., “Performance in GPU Architectures.: Potentials & Distances”, inproc. Workshop on Duplicating, Deconstructing, & Debunking at International Symposium on Computer Architecture (ISCA-38), June  2011.

 

46.  Samie, F., Baniasadi, A., “Power and Frequency Analysis for Data and Control Independence in Embedded Processors” in proc. of the Power Measurement and Profiling workshop held in conjunction with the Second International Green Computing Conference (IGCC'11), July 2011.

 

47.  Kishani, M., Baniasadi, A., Pedram, H., “Using Silent Writes in Low-Power Traffic-Aware ECC”, in proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2011),September 2011.

 

48.  Taherian, M., Baniasadi, A., Noori, H., “Instruction and Data Cache Peak Temperature Reduction Using Cache Access Balancing in Embedded Processors”, in proc. ACS/IEEE International Conference on Computer Systems and Applications (AICCSA 2011), December 2011.

 

49.  Hajkazemi, A., Baniasadi, A., “HICPA: A Hybrid Low Power Adder for High-Performance Processors”, in proc. of LASCAS March 2012.

 

50.  Farahani, M.,  Eslami, F., Baniasadi, A., “Application Specific Low Leakage Data Cache for Embedded Processors”, in proc. of the 16th CSI Symposium on Computer Architecture & Digital Systems (CADS-38), May 2012.