Refereed Journal Publications

 

1. Baniasadi, A., "Power-Aware Branch Predictor Update", IEE Proceedings Computers & Digital Techniques. Volume 152, Issue 5, pp. 585-595, September 2005.

 

2. Baniasadi, A., "Energy-Aware Dynamic Resource Allocation Heuristics for Clustered Processors”, IEEE Canadian Journal of Electrical and Computer Engineering. Volume 31, Number 3, pp. 117-125, summer 2006.

 

3.Atoofian, E., Baniasadi, A., "Improving energy-efficiency by bypassing trivial computations ", IEE Proceedings Computers & Digital Techniques. Volume 153, Issue 5, pp. 313-322 September 2006.

 

4.Aasaraai, K., Baniasadi, A.,”Low-Complexity Perceptron Branch Predictor”, ASP Journal of Low Power Electronics. Volume 2, Number 3, pp. 333-341, December 2006.

 

5.Atoofian, E., Baniasadi, A., and Aasaraai, K., "Exploiting Speculation Cost Prediction in Power-Aware Applications", ASP Journal of Low Power Electronics. Volume 3, Number 1, pp. 45-53, April 2007.

 

6.Atoofian, E., Baniasadi, A., "Speculative Trivialization Point Advancing in High Performance Processors", Journal of Systems Architecture Volume 53, Number 9, pp. 587-601, September 2007.

 

7.Jokar Deris, K., Baniasadi, A., "Investigating Cache Energy and Latency Break-even Points in High Performance Processors", ACM SIGARCH Computer Architecture News Volume 35, Issue 4, September 2007.

 

8.Atoofian, E., Baniasadi, A., "Using Supplier Locality in Power-Aware Interconnects and Caches in Chip Multiprocessors", Journal of Systems Architecture, Volume 54, Number 5, pp. 507-518, May 2008.

 

9.Baniasadi, A., Salamat, B. and Jokar Deris, k., “Power-Aware Scoreboard Alternatives for Multimedia Processors”, Journal of Microprocessors and Microsystems, February 2009.

 

10.Jokar Deris, K., Baniasadi, A., "Power-Aware BTB Alternatives for Modern Processors", International Journal of Computers and Electrical Engineering, September 2008.

 

11.Nikoubin, T., Baniasadi, A., Eslami, F.,  and Navi, K.,  “Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid CMOS Logic Style” Journal of Low Power Electronics  2009, Volume 5,  Number 4,  December 2009

 

12.Jooya, A., Baniasadi, A.,  and Analoui, M., “History-Aware, Resource-Based Dynamic Scheduling For Heterogeneous High-Performance Multi-core Processors”,  IET Computers & Digital Technique 2011, Volume 5, Number 4, July 2011