Babak Zakeri
MASc Student of ECE Department of University of Victoria
ReCoEng lab (Laboratory of Reconfigurable Computing Engineering)
Email Address: babak.zakeri@gmail.com
Phone: +1-250-885-7509
(to see my full CV click here)
Education:
Present: MASc in Electrical Engineering in University of Victoria, Victoria, BC, Canada, Started in Sep 2009.
Supervisor: Dr. Mihai Sima
MSc in Digital-Electronics from Sharif University of Technology, Tehran, Iran, June 2005 to February 2008. Project: Differential Power Analysis Attack Resistant Implementation of AES Algorithm on FPGA using Masking Methods
Supervisor: Dr. M. Salmasizadeh
BSc in Electrical Engineering-Electronics from University of Tehran, Tehran, Iran, June 2000 to June 2005. Project: Testing, debugging and implementation of two CPU cores. Designing of an MPEG video decoder, implementation and testing the code as a golden model on Virtex II and Virtex IV FPGAs.
Supervisor: Dr. M. Movahedin
Published Papers:
B. Zakeri, M. Salmasizadeh, A. Moradi, M. Tabandeh, and M.T. Manzuri Shalmani. Compact and Secure Design of Masked AES S-box. In Sihan Qing, Hideki Imai and Guilin Wang, editors. International Conference on Information and Communications Security ?ICICS 2007, 9th International Conference, , Sofitel Zhengzhou, Zhengzhou, China, 12-15, Dec 2007, Proceedings, volume 4861 of Lecture Notes in Computer Science, pages 216-229. Springer, 2007.
Work Experience:
Parseh semiconductor, March 2005 to April 2006, Tehran, Iran
Job description:
Testing, debugging and implementation of two CPU cores. Designing of an MPEG video decoder, implementation and testing the code as a golden model on Virtex II and Virtex IV FPGAs.
Simulation and debugging of two CPU cores
Preparing a compatible MPEG video decoder C code for Sparc architecture
Designing, debugging and implementation of some external peripherals (Memory, UART, ...) for the CPU cores.
Emulation of the MPEG decoder as a golden model for the processors.
Micro-Controller lab of Sharif University of Technology, September 2006 till December 2006, Tehran, Iran
Job Description: Lab TA
Electronics Research Center of Sharif University of Technology, Dec. 2006 to March. 2008, Tehran, Iran
Job description:
Researching as MSc thesis on AES algorithm, attacks against it and attack resistant implementations.
Presenting a compact and secure hardware implementation of AES encryption algorithm on Xilinx FPGA series.
Alborz Sanat Kavir Co., July 2007 till July 2008, Tehran, Iran
Job description:
Digital designer of a high voltage inverter design project for traction motor control for Tehran’s underground railway.
HDL code development on Altera FPGA series.
SAMA Co., Dec. 2007 till May 2008
Job description:
Digital designer of a digital TV design project.
HDL code development on Actel anti-fuse FPGA series.
University of Victoria, October 2009 till December 2009
Job description: TA of Computer Architecture lab
University of Victoria, February 2010 till April 2010
Job description: TA of Electronic Circuits I
Project (Thesis) Currently Involved:
Studying the Vulnerability of a certain Stream Cipher Algorithm against Side-Channel Attacks.
Main Expertise:
Design, Simulation, Synthesis, Implementation and Emulation of HDL (Verilog/VHDL) codes on Xilinx and Altera FPGAs.
Side-Channel Attacks regarding the FPGA Implementations of Cryptographic Algorithms.
Research Interests:
Side-Channel Attacks of Cryptographic Algorithms on Hardware Implementations, FPGA Architecture, Dynamic Partial Reconfiguration in FPGAs, Improvement of FPGA Compilers
Nationality:
I'm Persian (Iranian) from Iranian Parents who are originally from Turkish part of Iran which makes me capable of understanding Azari (A branch of Turkish language) other than Farsi, my native language :].
I'm also considered British since I was born and lived in UK for a few years.
Interests and Hobbies:
Thinking, Work, Music, Hanging out with Friends, Analytical and Archetypal Psychology, DotA of Warcraft, and maybe paiting soon :].
updated in December 2010