Signals from Virtual Container Processor

Pause Signal

If a pause signal is asserted from the VCP, HDLC Compare, Shift Register, Bytestuffer and FCS pause what they are doing until the Pause signal is unasserted.

Drop Packet Pulse

If a dropPacketPulse signal asserted from the VCP, the HDLC Compare resets itself and sends out a signal to the Shift Register, Bytestuffer and FCS, which effectively resets each module, dropping any packet information currently being processed.