The Frame Check Sequence register calculates a two byte value used for error checking.
Each data bit is passed to the Frame Check Sequence (FCS) which controls FCS calculations and sending of the FCS bytes to the Bytestuffer for processing. The FCS is calculated over the serial bits as they enter, and then the complement of the resulting FCS is sent to the HDLC Compare module. The FCS detects errors in the received frame, with a high level of confidence. The polynomial used in our implementation is x^16 + x^12 + x^5 + 1.
After an eof is received from HDLC Compare, the least significant byte followed by the most significant byte (MSB)of the FCS are sent to HDLC Compare for processing.
The receiver has no way of determining that it has finished calculating the received FCS until it detects the Flag Sequence. Therefore, the FCS was designed so that a particular pattern results when the FCS operation passes over the complemented FCS. A good frame is indicated by this "good FCS" value.