Frame Processing



Overview

HDLC is a data link protocol that uses a unique byte sequence to delimit the start and end of each protocol description unit (PDU) transported by the data link layer service.

Each piece of data is encapsulated in an HDLC frame by adding a trailer and a header. The header contains an HDLC address and an HDLC control field. The trailer is found at the end of the frame, and contains a Frame Check Sequence (FCS) shift register for error checking. In HDLC, frames are delimited by a sequence of bits known as a "flag". The flag sequence is a unique 8-bit sequence of the form 0111 1110. HDLC flag sequences are transmitted between each frame and whenever there is no data to be transmitted.


Processing Data from Input Queue

Data bytes are removed from the Input Queue by the byte passer and are loaded into both a Shift Register for eventual error checking and a High-Data Link Control (HDLC) Compare module. Data is dequeued from the Input Queue only when an end of frame (eof) bit is present within the Flag Queue. This signifies that at least one entire frame of data is present within the Input Queue. As data bytes are being dequeued from the Input Queue the byte passer checks the corresponding eof flag. If the eof flag is set, then the last data byte is processed followed by the bytes from the FCS. A pulse from the VCP to the HDLC Compare module is sent when a packet is to be dropped.

The design of HDLC Processing was broken into four main sections. Click on a section below to get more information.