The input of our design is interfaced using the PL3 standard. PL3 is a
standard which provides the interface for the interconnection of Physical
Layer (PHY) devices to ATM/Link layer devices implementing frame based ATM.
The data bus takes the data being passed and stores it in an input buffer
/queue. The handshaking signals that are used signal the end of a packet
(EOP), the start of a packet (SOP), a transmitted error (ERR), parity
(PRTY) and others. There are also signals from the PHY (our device) to
the link layer device specifying if the input buffer on our device is full
or not (DTPA). If the input buffer is full, transmission to our device
will be halted until there is room. This will not result in a loss of
data sequence, so we do not have to worry about data being dropped on the
As we can see above, when the Start of Packet signal (sop) is asserted,
the data on the bus represents the first 4 bytes of the packet. From
this point on, until the End Of Packet signal (eop) is asserted, each
clock cycle contains the next 4 bytes of the packet on the data bus.
Of course, all this is only valid when the enable signal is asserted low.
When the EOP signal is asserted, the data bus holds the last bytes of the
frame. Since not all frames are multiples of 4 bytes, this last
transmission may have only 1 to 4 bytes of valid data. The number of
invalid bytes is determined by the Mode signal (tmod). For example, in
the above figure the value of TMOD is "11" which represents 3. This means
that there are 3 invalid bytes and therefore only the first byte
(31 downto 24) is valid. Similarly, a TMOD of "01" would represent 1
invalid byte and the first 3 bytes (31 downto 8) are valid.