Queue Handler Interconnect


The x^43 + 1 scrambler that is implemented in the queue handler entity is constructed for security. Each VC-4 must be scrambled in correct sequence with other VC-4's and scrambled in its entirety. The scrambler is never reset.

In addition, one byte of the Path Overhead for each VC-4 is the 8-bit Bit-Interleaved Parity calculated over the previous VC-4. Thus, the BIP calculated over a VC-4 must be made available to the subsequent VC-4 before that VC-4 can be processed in its entirety.

An overview of Queue Handler interconnections can be seen below.

Required Signals

There are four signals propagating from each VC-4 to the subsequent VC-4, or from Queue Handler N to Queue Handler N+1 (Queue Handler 16 would send these four signals to Queue Handler 1 to complete the circle). Two signals propagate in the opposite direction, from Queue Handler N+1 to Queue Handler N (Queue Handler 1 would send these two signals to Queue Handler 16 to complete the circle).

In the following discussion we will discuss the signals that exist between Queue Handler 1 and Queue Handler 2, which will be called QH1 and QH2 respectively. This scenario can be extended to the rest of the Queue Handlers and is shown below.

BIP Signals

The first two of these signals propagating from QH1 to QH2 are BIP and BIP_valid_flg. BIP is an 8-bit bus that carries the BIP of the VC-4 from which it originates. BIP_valid_flg indicates a valid that the BIP is valid for the last processed VC-4.

When QH2 requires the BIP from QH1 to process its active queue, it checks to see if the BIP_valid_flg is asserted. If so, QH2 reads the BIP from the BIP bus and then pulses BIP_read high to indicate that QH1 need no longer hold the current BIP value. Upon receiving a pulse on BIP_read, QH1 deasserts the BIP_valid_flg.

Scrambler State Signals

An identical situation exists for scrambler_state, a 43 bit bus that contains the scrambler state after the active queue has been scrambled. Before QH2 processes the first byte of Path Overhead, it must receive the scrambler state from QH1. QH1 must completely finish processing its active queue before being able to provide the final scrambler state and assert the scrambler_state_valid_flg. When QH2 sees scrambler_state_valid_flg asserted, it reads the scrambler_state from Q1 and then pulses scrambler_state_read high. Upon receiving a pulse on scrambler_state_read, QH1 deasserts the scrambler_state_valid_flg.

This means there can be no overlap in the time required to process active queue for the next STM-16 frame. The total processing time must be allowed for each queue before the end of the current STM-16 frame.