Input State Machine



Overview

The input state machine is the controller used to accept data from a transmitter using the PL3 interface. The state machine performs the functions of the PHY side of the interface.



First, the controller makes sure that the enable signal is low. If not, nothing is done and none of the signals are looked at. If the enable signal is low, the input signals are looked at. The first signal to be looked at is the End Of Frame signal. If it the end of the frame, the TMOD signal is looked at to see how many bytes are invalid. The valid bytes are then put on the data bus to the queue. If it is not the end of a frame, all four bytes are placed on the data bus to the queue. The appropriate signals to the queue are also asserted.

Note that the Start of Packet is not looked at in this stage. This is because a start of packet behaves the same as a normal write. As long as the enable is low, all four bytes are valid and written to the queue.