The following are some of the main requirements for this portion of the SDH framer design:- 16 VC-4's must be created every 125µs regardless of whether or not data is available to transmit
These requirements taken together imply that each VC-4 must be scrambled before being byte-interleaved and because scrambling must happen sequentially, at least 15 of the 16 VC-4's in the STM-16 frame must be completely scrambled before the STM-16 frame requires that data to be available. Thus, it is easier to make sure all sixteen VC-4's are ready by the time they are required byte-interleaved by the STM-16 frame.
This means that any design must be able to store at least 16 * ( 261 * 9 + 9 ) bytes of data to store all 16 VC-4's, or approximately 295 KB of data. We did not see any way to avoid this situation, so our design, if implemented, would require quite a bit of memory.
In order to accommodate both the 16 VC-4's that have been completed (including scrambling) and are currently being byte-interleaved into an STM-16 frame, and the 16 VC-4's that are being constructed for the next STM-16 frame, a total of 32 queues are required. Further, it is intuitive to group the queues in pairs; one queue of the pair actively accepting data for the next STM-16 frame and the other containing a complete, scrambled VC-4 that feeds the current STM-16 frame byte by byte.
The diagram below shows the general setup for the Virtual Container Processor. For more information on how this works, click either of the outlined sections below.