The Shift Register is loaded from the Input Queue and shifted out one bit at a time to the Frame Check Sequence register.
The Shift Register is loaded with a byte of data from the Input Queue when a load signal is present. Once loaded the Shift Register always does a logical shift right because it was designed with least significant byte (LSB) first serial communications in mind. A shift takes place each clock pulse until all eight bits are shifted out of the Shift Register. A zero is shifted into bit seven of the register as the Shift Register shifts a bit at a time into the FCS register.