Input Controller Problem
The input controller portion of the
design must be able to accept incoming packets from a network. Secondly, the
input controller must send the received packet to a memory module. Thirdly, the
input controller portion of the design must receive the packet location
information from the memory module and send it to the token buffer.
For the purposes of the High Speed
Memory Design, a packet is considered 8 bits in
Input Controller Design
The Token Buffer portion of the design is broken into three distinct tasks:
Receiving the packet from the network.
Sending the received packet to a memory module.
Sending the packet address location to the token buffer.
Receiving the Packet
The input controller must be able to
receive all packets it gets from the network. Once the input
controller gets the packet it must send it to the appropriate memory module.
The input controller must select a
memory module which is not busy or full. Once the input controller has found a
memory module, it will send the packet that it has just received from the
network to the memory module.
the Packet Address Location
The input controller must now wait until it receives the packet address location from the appropriate memory module. Once, the packet address location is received from the memory module is then sent to the token buffer.
Here are some Block Diagrams
© RAM Memory Solutions, 2001