The Output Controller is one of the
four key components of the Switch Buffer Memory.
It must be able to quickly communicate with other modules in order to
perform significant tasks. The
Output Controller must determine how many packets are requested for output. The Output Controller must also be able to receive the
address information of the desired data packet from the Token Buffer.
In addition, the Output Controller must also retrieve the data packet
form the Memory Module. And finally, the Output Controller must output the respective
data packet as requested.
Controller Design Solution
The Output Controller is broken down into 2 distinct components:
Finite State Machine Module
two components form the Output Controller.
In addition, the Finite State Machine Module is instantiated 5 times to
achieve efficient and multiple reads from memory.
the Number of Packets Requested
module Main is responsible for determining the number of packets requested.
As in any network switch, there must be a request, from somewhere, to
output a packet. In this design, it
was determined that an input line would be externally set to a value
corresponding to the number of packets requested.
As a result, this input is hard wired to the Main module.
module Main is responsible for alerting the overall system of a packet request.
Main polls this input line, and passes its value to another module within
the Memory Component called the Token Buffer. The Token Buffer then knows, that it must transmit this many
tokens back to the Output Controller. More
specifically, these tokens are sent directly to the Finite State Machine module.
Tokens contain the address information for any given packet.
The Finite State Machine module is responsible for reading any packet out of memory and then transmitting it as output. The FSM receives tokens, namely, the address information of the packet it must read from memory. It then takes this token and breaks it into two parts – the number of the memory module it is stored in, and the address location where it is stored. It then sends the packet address to the appropriate memory module. The FSM waits until the memory module is ready for reading. As soon as the memory module is ready, the packet is read from the memory module and output immediately by the FSM. This process is repeated forever, but only when the Token Buffer supplies a token.
Here are some Block Diagrams
© RAM Memory Solutions, 2001