The problem at hand is the design of a high-speed, multi-port memory for a network switch. High performance network routers and/or switches rely on the availability of several key components for operational purposes. One crucial component is the availability of fast multi-ported memory. This memory must be able to support one write and several read operations simultaneously. This is in contrast with normal memory systems that only support one write or one read operation. This is the convention used commonly today.
It is our intention as
a group, to find an efficient, unique, and new solution for the above mentioned
problem. More specifically, the
following is a list of objectives that we wish to meet by the end of this
· Be able to Write a packet into the Memory Control System and simultaneously be able to Read a packet from the Memory Control System.
· Be able to perform multiple packet reads from the Memory Control System.
· Be able to output one or more packets out of the overall system.
· Be able to able to implement the design in software using a Hardware Description Language such as VHDL.
Be able to simulate the design in VHDL.
These objectives are crucial to the success of our project. It is our intention to meet each and every one of the objectives by the end of the ELEC/CENG 499a course.
© RAM Memory Solutions, 2001