FFT Architeture
Data and M athematical O peration Architecture
Design of Processor in Verilog
Data and Mathematical Operation Architecture
The following reasons are why we pick floating point arithmetic over fixed point arithmetic:
 32 bit floating point arithmetic is commonly used throughout the audio industry , because it lends itself to simple digital signal processes like gain change and mixing .
 Floating point is easy to implement, fixed point must handle scaling issues.
 Greater Dynamic Range .
 High precision and reduced noise from operations on data.
Figure 9 shows IEEE 754 standard floating point arithmetic.
Sign 
Exponent 
Significand 
S 
8 bits  E 
23 bits  C 
Figure 9: IEEE Single Precision Data Format
Floating point adder
Here are the steps for adding or subtracting two numbers

Compare the exponents of two numbers for ( or ) and calculate the absolute value of difference between the two exponents (). Take the larger exponent as the tentative exponent of the result.

Shift the s ignificand of the number with the smaller exponent, right through a number of bit positions that is equal to the exponent difference. Two of the shifted out bits of aligned s ignificand are retained as guard (G) and round (R) bits. So for p bit significand, the effective width of aligned significand must be p + 2 bits. Append a third bit, namely the sticky bit (S), at the right end of the aligned significand. The sticky bit is the logical OR of all shifted out bits.

Add or subtract the two signedmagnitude significands using a p + 3 bit adder. Let the result of this is SUM

Check SUM for carry out (C out ) from the MSB position during addition. Shift SUM right by one bit position if a carry out is detected and increment the tentative exponent by 1. During subtraction, check SUM for leading zeros. Shift SUM left until the MSB if the shifted result is a 1. Subtract the leading zero count from tentative exponent. Evaluate exception condition, if any.

Round the result if the logical condition Rh(M 0 +Sh) is true, where M 0 and Rh represent the pth and (p+1)st bits from the left end of the normalized significand . New sticky bit (Sh) is the logical OR of all bits towards the right of the Rh bit. If the rounding condition is true, a 1 is added at the pth bit (from the left side) of the normalized significand. If p MSB of the normalized significands are 1's, rounding can generate a carryout. In the case, normalization (step 4) has to be done again.
Figure 8 shows the flow chart of floating point addition.
Figure 10: Floating Point Addition
Floating point multiplier
Here are the steps for multiplying two numbers

Calculate the tentative exponent of the product by adding the biased exponents of the two numbers, subtracting the bias, (). Bias is 127 and 1023 for single precision and double precision IEEE data format respectively.

If the sign of two floating point numbers are the same, set the sign of product to e+', else set it to e'.

Multiply the two significands. For p bit significand, the product is 2p bits wide (p, the width of v data field, is including the leading hidden bit (1)). Product of significands falls within range.

Normalize the product if MSB of the predicts is 1 (i.e. product of ), by shifting the product right by 1 bit position and incrementing the tentative exponent. Evaluate exception conditions, if any.

Round the product if R( M o +S) is true, where M 0 and R represent the pth and (p+1)st bits from the left end of the normalized product. Sticky bit (Sh) is the logical OR of all bits towards the right of the R bit. If the rounding condition is true, a 1 is added at the pth bit (from the left side) of the normalized product. If all p MSBs of the normalized product are 1's, rounding can generate a carryout. In that case, normalization (step 4) has to be done again.
Figure 9 shows the flow chart of floating point multiplier.
Figure 11: Floating Point Multiplication 