FFT Architeture
Data and M athematical O peration Architecture
Design of Processor in Verilog
FFT Architeture
The data I/O and control signal pins are illustrated in Figure 1
Figure 4: Top Level Block Diagram of FFT
The DFT X(k) of an Npoint sequence x(n) is defined by
To derive the radix4 decimationinfrequency algorithm, the above equation can be split into 4 small parts of DFT. The equation becomes
The above equations can be expressed as the following matrix:
For 16point values, the pipeline DFT needs 2 stages to generate proper outputs, and the number of stages can be calculated by use the following equation:
Number of stage = log 4 16 = 2 stages
Figure 5: Pipelined DFT
Figure 6: Radix4 butterfly
Figure 7: Commutator Switch for first stage
Figure 8: Switch Instances
The BF1 and BF2 are computation elements as shown in figure 6.
The first commutator switch, figure 7, distributes to each output line every 4 cycle. The rest of commutator switches repeats the pattern shown as figure 8. Then, each output line passes through different parallel delay commutator. Each delay path has different delay (figure 5). In this way, the computational element at each stage can receives values at same time, and the proper calculation can be done correctly at each stage.
