[1] Y. N. Chang and K. K. Parhi, gAn Efficient Pipelined FFT Architecture,h IEEE Transactions on Circuits and Systems II , vol. 50, NO. 6, June 2003.

[2] Y. Jung, H. Y, and J. Kim, gNew Efficient FFT Algorithm and Pipeline Implementation Results for OFDM/DMT Applications,h IEEE Transactions on Consumer Electronics, vol. 49, NO 1, February 2003.

[3] E. E. Swartzlander Jr., W. K. Young, and S. J. Joseph, gA Radix 4 Delay Commutator for Fast Fourier Transform Processor Implementation,h IEEE Journal of Solid-State Circuits, vol. sc-19, NO. 5, October 1984.

[4] E. E. Swartzlander Jr., gVLSI Signal Processing System,h Kluwer Academic Publishers, 1986, pp. 125-131.

[5] L. R. Rabiner and B. Gold, gTheory and Application of Digital Signal Processing,h Prentice-Hall, Inc., 1975, pp. 356-380, pp. 602-612.

[6] A. Berkeman, V. Owall, and M. Torkelson, gA Low Logic Depth Complex Multiplier Using Distributed Arithmetic,h IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000.

[7] S.Kobayashi and G.P Fettweis, gA new approach for block-floating-point arithmetic,h ICASSP '99. Proceedings., Volume: 4 , 15-19 March 1999.

[8] S. Kobayashi, S.Y. Lee, T. Kino, I. Kozuka and T. Tokui, gAudio application implementations on a block-floating-point DSP,h IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02), 16-18 Oct. 2002, Pages:51 ? 56.


Copyright (C)2004 CDS Technology Inc., All rights reserved.