Synopsys

• Getting acquainted with Synopsys
• Objectives
• Sample project
• Low level component
• Top level description
• Simulation command file
• Testbench and its command file

VHDL

• Overview
• 1-bit latch
• 2-input and with a sensitivity list
• 2-input and with a wait statement
• 4-bit latch using behavioral description
• 4-bit latch using structural description, named signal association, and architecture configurations
• 4-bit latch using structural description, positional signal association, and architecture configurations
• 4-bit latch using structural description, positional signal association, and a separate configuration declaration
• 8-bit latch using structural description
• 4-bit equality comparator using a dataflow description
• Half-adder using dataflow description
• Tri-state driver
• Tri-state driver with a package
  
• A testbench for a free-running counter
• An RS-flip-flop using concurrent signal assignments
• A testbench for a D-flip-flop

• Language basics
  
• Signal integrator
• Complex number multiplier
• Small_int type, taking values in the range 0 to 255
• Eight_bit subtype, taking values in the range -128 to 127
• An RS-flip-flop using two processes. Here is a synopsys command file to use for testing it.
  
• Package with some constants and subtypes

• Combinational modeling
  
• Combinational logic using simple concurrent signal assignment statements
• Combinational network using conditional concurrent signal assignment statements
• A decoder using selective concurrent signal assignment statements
• 4-1 mux using an IF statement
• Address decoder using a CASE statement
• Another address decoder using a CASE statement
• Full adder using a CASE statement
• ALU using a CASE statement
• A counter that starts from 0 and increments mod 16 on each rising edge of the clock
• A counter that starts from 0 and increments mod 16 on each rising edge of the clock with a reset and stop inputs
• A circuit that compresses a bit_vector by bit-wise XORing all its elements
• A circuit that counts the ones in a vector
• A procedure to be used in defining a set of stimuli to a D-flip-flop, using positional association for parameters
• A more flexible procedure to be used in defining a set of stimuli to a D-flip-flop, using named association for parameters
• A package declaration that defines a function that ands two unsigned numbers
• A package hat defines a function that converts a natural number to unsigned
• A two-input and gate with a specified delay and then instantiating it in building a four-input and gate
• An and gate with different loading using selected signal assignment statement
• An and gate with rise and fall times, which depend on loading
• Entity declaration for an ALU with a variable word width
• Generating a wider ALU from a small one
• Generating a wider ALU from two small ones
• A process that reads a text line from a file and parses them into internal variables
• A process that forms a text line from into internal variables and writes it to a file
• A testbench that rads a set of stimuli to a D-flip-flop from a file
  

• Sequential modeling
  
• Definition of 8 states in a package using an enumerated data type, using gray encoding for states
• Definition of 8 states in a package using a constant for each state, using Johnson state encoding for states
• Definition of 8 states in a package, using an integer for each state.
• An odd parity checker as an FSM using VHDL. Coding style: One process Mealy
• An odd parity checker as an FSM using VHDL. Coding style: Two processes Mealy
• An odd parity checker as an FSM using VHDL. Coding style: Three processes Mealy
• An odd parity checker as an FSM using VHDL. Coding style: One process Moore
• An odd parity checker as an FSM using VHDL. Coding style: Two processes Moore
• An odd parity checker as an FSM using VHDL. Coding style: Three processes Moore
• An odd parity checker as an FSM using VHDL. Sample testbench
• An FSM using VHDL, using Johnson state encoding for states
• An FSM with Moore and Mealy outputs
• An n-bit binary up/down counter with synchronous preset and clear
• An n-bit gray up/down counter with synchronous clear
• A parallel to serial converter
• A negative edge-triggered flip-flop with select input
• A positive edge-triggered flip-flop with asynchronous set and clear
  
• A D-FF with setup, hold, and delay times
• A shift register to perform shift right, shift left, and load
• A ROM to build a squaring circuit
• An n-bit address, m-bit word size, dual-port RAM
• An n-bit address, m-bit word size, single-port RAM
• Synthesis basics
  
• A mux using selective concurrent signal assignment statements
• Assignment statements
• Other assignment statements
• Other assignment statements
• Other assignment statements
• A for loop
• A DEMUX
• An if statement and its synchronized version
  
• Another if statement
• Another if statement
• Another if statement
• A priority encoder
• A level-triggered, with a delay, latch
• Another if statement
• Other assignment statements
• An increment-by-one circuit
• A mus using a case statement
  
• A 3-to-8 decoder with an enable
• A case statement
• A case statement
• Another if statement
• A wait statement
• A procedure
  
• An FSM with Moore and Mealy outputs
• A portion of an FSM
• Tristate elements
• Other tristate elements
• Other tristate elements

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