/* ".synopsys_dc.setup" Initialization File for Dc_Shell and Design_Analyzer The variables in this file define the behavior of many parts of the Synopsys Synthesis Tools. Upon installation, they should be reviewed and modified to fit your site's needs. Each engineer can have a .synopsys file in his/her home directory or current directory to override variable settings in this file. Each logical grouping of variables is commented as to their nature and effect on the Synthesis Commands. Examples of variable groups are the Compile Variable Group, which affects the designs produced by the COMPILE command, and the Schematic Variable Group, which affects the output of the create_schematic command. You can type "help _variables" in dc_shell or design_analyzer to get help about a group of variables. For instance, to get help about the "system" variable group, type "help system_variables". You can also type "help ", to get help on the that variable's group. */ /* Enable debug output on fatal */ if (arch == "sparc") { set_unix_variable(SYNOPSYS_TRACE, "") } /* Temporary fix for the LMC_HOME variable- set it to an empty string */ if (get_unix_variable("LMC_HOME") == "") { set_unix_variable("LMC_HOME", "") } /* Site-Specific Variables These are the variables that are most commonly changed at a specific site, either upon installation of the Synopsys software, or by specific engineers in their local .synopsys files. */ /* from the System Variable Group */ link_force_case = "check_reference"; link_library = {"*" your_library.db} ; search_path = {. /CMC/tools/synopsys + "/libraries/syn"} ; target_library = {your_library.db} ; synthetic_library = {} ; command_log_file = "./command.log"; designer = "" ; company = ""; find_converts_name_lists = "false"; symbol_library = {your_library.sdb} ; /* from the Schematic Variable Group */ if( arch == "hp700" ) { plot_command = "lp -d" ; /* from the Plot Variable Group */ } else { plot_command = "lpr -Plw" ; } view_command_log_file = "./view_command.log" ; /*from the View Variable group*/ if ( arch == "hp700" ) { text_print_command = "lp -d" ; } else { text_print_command = "lpr -Plw" ; } /* System Variable Group: These variables are system-wide variables. */ arch_init_path = synopsys_root + "/" + arch + "/motif/syn/uid" ; auto_link_disable = "false" ; auto_link_options = "-all"; uniquify_naming_style = "%s_%d" ; verbose_messages = "true"; echo_include_commands = "true" ; preserve_subshells = {"hdl_shell_exec"} ; suppress_errors = {} ; change_names_update_inst_tree = "true" ; change_names_dont_change_bus_members = "false" ; default_name_rules=""; /* Compile Variable Group: These variables affect the designs created by the COMPILE command. */ compile_assume_fully_decoded_three_state_busses = "false" ; compile_fix_multiple_port_nets = "false" ; compile_no_new_cells_at_top_level = "false"; compile_preserve_sync_resets = "false"; compile_ignore_area_during_inplace_opt = "false" ; compile_ignore_footprint_during_inplace_opt = "false" ; compile_dont_touch_annotated_cell_during_inplace_opt = "false" ; compile_ok_to_buffer_during_inplace_opt = "false" ; compile_disable_area_opt_during_inplace_opt = "false"; compile_update_annotated_delays_during_inplace_opt = "true"; compile_instance_name_prefix = "U" ; compile_instance_name_suffix = "" ; compile_negative_logic_methodology = "false" ; compile_disable_hierarchical_inverter_opt = "false"; compile_use_fast_delay_mode = "true" ; compile_use_fast_sequential_mode = "false" ; compile_use_low_timing_effort = "false" ; compile_preserve_subdesign_interfaces = "false"; port_complement_naming_style = "%s_BAR" ; compile_implementation_selection = "true"; compile_mux_no_boundary_optimization = "false"; compile_create_mux_op_hierarchy = "true"; reoptimize_design_changed_list_file_name = ""; reoptimize_design_disable_area_opt_during_postlayout_opt = "false"; alias compile_inplace_changed_list_file_name \ reoptimize_design_changed_list_file_name actel_seq_opto = 0; actel_qbar_opto = 0; /* Synthetic Library Group: These variable affect synthetic library processing. */ synlib_dont_get_license = {}; synlib_evaluation_mode = "false" ; synlib_optimize_non_cache_elements = "true" ; synlib_model_map_effort = "medium"; synlib_disable_limited_licenses = "true"; synlib_sequential_module = "default"; cache_read = { "~" } ; cache_write = "~" ; cache_read_info = "false"; cache_write_info = "false"; cache_file_chmod_octal = "666"; cache_dir_chmod_octal = "777"; /* Insert_Test Variable Group: These variables affect the designs created by the INSERT_TEST command. */ insert_test_design_naming_style = "%s_test_%d" /* insert_test_scan_chain_only_one_clock = "false" Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ test_clock_port_naming_style = "test_c%s" test_scan_clock_a_port_naming_style = "test_sca%s" test_scan_clock_b_port_naming_style = "test_scb%s" test_scan_clock_port_naming_style = "test_sc%s" test_scan_enable_inverted_port_naming_style = "test_sei%s" test_scan_enable_port_naming_style = "test_se%s" test_scan_in_port_naming_style = "test_si%s%s" test_scan_out_port_naming_style = "test_so%s%s" test_non_scan_clock_port_naming_style = "test_nsc_%s" test_default_min_fault_coverage = 95; insert_test_map_effort_enabled = TRUE test_disable_constraint_smart_insert = "false" test_isolate_hier_scan_out = 0; /* Analyze_Scan Variable Group: These variables affect the designs created by the PREVIEW_SCAN command. */ test_preview_scan_shows_cell_types = "false" test_scan_link_so_lockup_key = "l" test_scan_link_wire_key = "w" test_scan_segment_key = "s" test_scan_true_key = "t" /* TestManager Variable Group: These variables affect the TestManager methodology. */ multi_pass_test_generation = "false"; /* TestSim Variable Group: These variables affect the TestSim behavior. */ testsim_print_stats_file = "true"; /* Test DRC Variable Group: These variables affect the check_test command. */ test_capture_clock_skew = "small_skew"; test_allow_clock_reconvergence = "false"; /* Test Variable Group: These variables affect the check_test, write_test_protocol and write_test command. */ test_default_delay = 5.0; test_default_bidir_delay = 55.0; test_default_strobe = 95.0; test_default_strobe_width = 0.0; test_default_period = 100.0; test_default_scan_style = "multiplexed_flip_flop" /* JTAG variable group (associated with the insert_jtag command): These variables are associated with JTAG synthesis. */ jtag_port_drive_limit = 6; jtag_manufacturer_id = 0; jtag_version_number = 0; jtag_part_number = 65535; jtag_test_data_in_port_naming_style = "jtag_tdi%s"; jtag_test_data_out_port_naming_style = "jtag_tdo%s"; jtag_test_mode_select_port_naming_style = "jtag_tms%s"; jtag_test_clock_port_naming_style = "jtag_tck%s"; jtag_test_reset_port_naming_style = "jtag_trst%s"; /* Create_Test_Patterns Variable Group: These variables affect the create_test_patterns command. */ /* from hikari on, the "atpg_keep_faults_data" variable is obselete atpg_keep_faults_data = "false" */ atpg_test_asynchronous_pins = "true" /* Write_Test Variable Group: These variables affect output of the WRITE_TEST command. */ write_test_input_dont_care_value = "X"; write_test_vector_file_naming_style = "%s_%d.%s"; write_test_scan_check_file_naming_style = "%s_schk.%s"; write_test_pattern_set_naming_style = "TC_Syn_%d"; write_test_max_cycles = 0; write_test_max_scan_patterns = 0; /* retain "tssi_ascii" (equivalent to "tds") for backward compatability */ write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"}; write_test_include_scan_cell_info = "true"; /* Schematic and EDIF and Hdl Variable Groups: These variables affect the schematics created by the create_schematic command, define the behavior of the DC system EDIF interface, and are for controlling hdl reading. */ bus_dimension_separator_style = "][" bus_naming_style = "%s[%d]" ; /* Schematic and EDIF Variable Groups: These variables affect the schematics created by the create_schematic command and define the behavior of the DC system EDIF interface. */ bus_range_separator_style = ":" ; /* EDIF and Io Variable Groups: These variables define the behavior of the DC system EDIF interface and define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE, etc. */ bus_inference_descending_sort = "true"; bus_inference_style = ""; write_name_nets_same_as_ports = "false"; /* Schematic Variable Group: These variables affect the schematics created by the create_schematic command. */ font_library = "1_25.font" ; generic_symbol_library = "generic.sdb" ; gen_max_ports_on_symbol_side = 0 ; duplicate_ports = "false" ; sheet_sizes = {A, B, C, D, E, infinite, mentor_maximum, sge_maximum}; single_group_per_sheet = "false" ; use_port_name_for_oscs = "true" ; gen_bussing_exact_implicit = "false" ; gen_cell_pin_name_separator = "/" ; gen_max_compound_name_length = 256 ; gen_show_created_symbols = "false" ; gen_match_ripper_wire_widths = "false" ; gen_show_created_busses = "false" ; gen_dont_show_single_bit_busses = "false" ; gen_single_osc_per_name = "false" ; gen_create_netlist_busses = "true" ; sort_outputs = "false" ; gen_open_name_prefix = "Open" ; gen_open_name_postfix = "" ; default_schematic_options = "-size infinite"; /* This setting makes gen use the old way to annotate schematics for everything except sheets, which is fast enough. */ annotation_control = 64 ; /* Plot Variable Group: These variables define the operating system and plotter interface to the Design Compiler. These should be set at installation time, if needed, and then changed only if you start using a new type of plotter. These four variables must be changed if you use a larger or smaller plotter or printer: plotter_maxx, plotter_maxy, plotter_minx, plotter_miny See the group of site-specific variables at the top of this file to set the name of your printer or plotter. */ plot_orientation = "best_fit" ; plotter_maxx = 584 ; plotter_maxy = 764 ; plotter_minx = 28 ; plotter_miny = 28 ; plot_scale_factor = 100 ; plot_box = "false" ; /* Io Variable Group: These variables define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE, etc. */ db2sge_output_directory = ""; db2sge_scale = "2"; db2sge_overwrite = "true"; db2sge_display_symbol_names = "false"; db2sge_display_pin_names = "false"; db2sge_display_instance_names = "false"; db2sge_use_bustaps = "false"; db2sge_use_compound_names = "true"; db2sge_bit_type = "std_logic"; db2sge_bit_vector_type = "std_logic_vector"; db2sge_one_name = "'1'"; db2sge_zero_name = "'0'"; db2sge_unknown_name = "'X'"; db2sge_target_xp = "false"; db2sge_tcf_package_file = "synopsys_tcf.vhd"; db2sge_use_lib_section = ""; db2sge_script = "" ; db2sge_command = "" ; equationout_and_sign = "*" equationout_or_sign = "+" equationout_postfix_negation = "true" lsiin_net_name_prefix = "NET_"; lsiout_inverter_cell = ""; lsiout_upcase = "true"; mentor_bidirect_value = "INOUT" ; mentor_do_path = "" ; mentor_input_output_property_name = "PINTYPE" ; mentor_input_value = "IN" ; mentor_logic_one_value = "1SF" ; mentor_logic_zero_one_property_name = "INIT" ; mentor_logic_zero_value = "0SF" ; mentor_output_value = "OUT" ; mentor_primitive_property_name = "PRIMITIVE" ; mentor_primitive_property_value = "MODULE" ; mentor_reference_property_name = "COMP" ; mentor_search_path = "" ; mentor_write_symbols = "true" ; pla_read_create_flip_flop = "false"; tdlout_upcase = "true"; xnfout_constraints_per_endpoint = "50" ; xnfout_default_time_constraints = true; xnfout_clock_attribute_style = "CLK_ONLY"; xnfout_library_version =""; xnfin_family = "4000"; xnfin_ignore_pins = "GTS GSR GR"; xnfin_dff_reset_pin_name = "RD"; xnfin_dff_set_pin_name = "SD"; xnfin_dff_clock_enable_pin_name = "CE"; xnfin_dff_data_pin_name = "D" ; xnfin_dff_clock_pin_name = "C" ; xnfin_dff_q_pin_name = "Q" ; /* EDIF Variable Group: These variables define the behavior of the DC system EDIF interface. */ bus_extraction_style = "%s[%d:%d]"; edifin_autoconnect_offpageconnectors = "false"; edifin_autoconnect_ports = "false"; edifin_dc_script_flag = ""; edifin_delete_empty_cells = "true"; edifin_delete_ripper_cells = "true"; edifin_ground_net_name = ""; edifin_ground_net_property_name = ""; edifin_ground_net_property_value = ""; edifin_ground_port_name = ""; edifin_instance_property_name = ""; edifin_portinstance_disabled_property_name = ""; edifin_portinstance_disabled_property_value = ""; edifin_portinstance_property_name = ""; edifin_power_net_name = ""; edifin_power_net_property_name = ""; edifin_power_net_property_value = ""; edifin_power_port_name = ""; edifin_use_identifier_in_rename = "false"; edifin_view_identifier_property_name = ""; edifin_lib_logic_1_symbol = ""; edifin_lib_logic_0_symbol = ""; edifin_lib_in_port_symbol = ""; edifin_lib_out_port_symbol = ""; edifin_lib_inout_port_symbol = ""; edifin_lib_in_osc_symbol = ""; edifin_lib_out_osc_symbol = ""; edifin_lib_inout_osc_symbol = ""; edifin_lib_mentor_netcon_symbol = ""; edifin_lib_ripper_bits_property = ""; edifin_lib_ripper_bus_end = ""; edifin_lib_ripper_cell_name = ""; edifin_lib_ripper_view_name = ""; edifin_lib_route_grid = 1024; edifin_lib_templates = {} ; edifout_dc_script_flag = ""; edifout_design_name = "Synopsys_edif"; edifout_designs_library_name = "DESIGNS"; edifout_display_instance_names = "false"; edifout_display_net_names = "false"; edifout_external = "true"; edifout_external_graphic_view_name = "Graphic_representation"; edifout_external_netlist_view_name = "Netlist_representation"; edifout_external_schematic_view_name = "Schematic_representation"; edifout_ground_name = "logic_0"; edifout_ground_net_name = ""; edifout_ground_net_property_name = ""; edifout_ground_net_property_value = ""; edifout_ground_pin_name = "logic_0_pin"; edifout_ground_port_name = "GND"; edifout_instance_property_name = ""; edifout_instantiate_ports = "false"; edifout_library_graphic_view_name = "Graphic_representation"; edifout_library_netlist_view_name = "Netlist_representation"; edifout_library_schematic_view_name = "Schematic_representation"; edifout_merge_libraries = "false"; edifout_multidimension_arrays = "false"; edifout_name_oscs_different_from_ports = "false"; edifout_name_rippers_same_as_wires = "false"; edifout_netlist_only = "false"; edifout_no_array = "false"; edifout_numerical_array_members = "false"; edifout_pin_direction_in_value = ""; edifout_pin_direction_inout_value = ""; edifout_pin_direction_out_value = ""; edifout_pin_direction_property_name = ""; edifout_pin_name_property_name = ""; edifout_portinstance_disabled_property_name = ""; edifout_portinstance_disabled_property_value = ""; edifout_portinstance_property_name = ""; edifout_power_and_ground_representation = "cell"; edifout_power_name = "logic_1"; edifout_power_net_name = ""; edifout_power_net_property_name = ""; edifout_power_net_property_value = ""; edifout_power_pin_name = "logic_1_pin"; edifout_power_port_name = "VDD"; edifout_skip_port_implementations = "false"; edifout_target_system = ""; edifout_top_level_symbol = "true"; edifout_translate_origin = ""; edifout_unused_property_value = ""; edifout_write_attributes = "false"; edifout_write_constraints = "false"; edifout_write_properties_list = {}; read_name_mapping_nowarn_libraries = {}; write_name_mapping_nowarn_libraries = {}; /* Hdl and Vhdlio Variable Groups: These variables are for controlling hdl reading, writing, and optimizing. */ bus_minus_style = "-%d"; hdlin_advisor_directory = "."; hdlin_hide_resource_line_numbers = FALSE; hdlin_reg_report_length = 60; hdlin_auto_save_templates = FALSE; hdlin_replace_synthetic = FALSE; hdlin_latch_always_async_set_reset = FALSE; hdlin_ff_always_sync_set_reset = FALSE; hdlin_ff_always_async_set_reset = TRUE; hdlin_check_no_latch = FALSE; hdlin_report_inferred_modules = "true"; hdlin_reg_report_length = 60; hdlin_translate_off_skip_text = false; hdlin_keep_feedback = FALSE; hdlin_keep_inv_feedback = TRUE; hdlin_infer_mux = "default"; hdlin_dont_infer_mux_for_resource_sharing = "true"; hdlin_mux_size_limit = 32; hdl_preferred_license = ""; hdl_keep_licenses = "true"; hlo_resource_allocation = "constraint_driven"; hlo_transform_constant_multiplication = "false"; hlo_minimize_tree_delay = true ; hlo_resource_implementation = "constraint_driven" ; hlo_share_common_subexpressions = true ; hlo_share_effort = low ; hlo_ignore_priorities = false; sdfout_top_instance_name = ""; sdfout_time_scale = 1.0; sdfout_min_rise_net_delay = 0.; sdfout_min_fall_net_delay = 0.; sdfout_min_rise_cell_delay = 0.; sdfout_min_fall_cell_delay = 0.; sdfout_write_to_output = "false"; sdfout_allow_non_positive_constraints = "false"; sdfin_top_instance_name = ""; sdfin_min_rise_net_delay = 0.; sdfin_min_fall_net_delay = 0.; sdfin_min_rise_cell_delay = 0.; sdfin_min_fall_cell_delay = 0.; sdfin_rise_net_delay_type = "maximum"; sdfin_fall_net_delay_type = "maximum"; sdfin_rise_cell_delay_type = "maximum"; sdfin_fall_cell_delay_type = "maximum"; site_info_file = synopsys_root + "/admin/license/site_info" alias site_info sh cat site_info_file hdl_naming_threshold = 20 template_naming_style = "%s_%p"; template_parameter_style = "%s%d"; template_separator_style = "_"; design_library_file = ".synopsys_vss.setup"; verilogout_equation = "false"; verilogout_ignore_case = "false"; verilogout_no_tri = "false"; verilogout_single_bit = "false"; verilogout_higher_designs_first = "FALSE"; verilogout_levelize = "FALSE"; verilogout_include_files = {}; verilogout_unconnected_prefix = "SYNOPSYS_UNCONNECTED_"; verilogout_show_unconnected_pins = "FALSE"; vhdlout_architecture_name = "SYN_%a_%u"; vhdlout_bit_type = "std_logic"; vhdlout_bit_type_resolved = "TRUE"; vhdlout_bit_vector_type = "std_logic_vector"; vhdlout_conversion_functions = {}; vhdlout_dont_write_types = "FALSE"; vhdlout_equations = "FALSE"; vhdlout_one_name = "'1'"; vhdlout_package_naming_style = "CONV_PACK_%d"; vhdlout_preserve_hierarchical_types = "VECTOR"; vhdlout_separate_scan_in = "FALSE"; vhdlout_single_bit = "USER"; vhdlout_target_simulator = ""; vhdlout_three_state_name = "'Z'"; vhdlout_three_state_res_func = ""; vhdlout_time_scale = 1.0; vhdlout_top_configuration_arch_name = "A"; vhdlout_top_configuration_entity_name = "E"; vhdlout_top_configuration_name = "CFG_TB_E"; vhdlout_unknown_name = "'X'"; vhdlout_upcase = "FALSE"; vhdlout_use_packages = {"IEEE.std_logic_1164"}; vhdlout_wired_and_res_func = ""; vhdlout_wired_or_res_func = ""; vhdlout_write_architecture = "TRUE"; vhdlout_write_components = "TRUE"; vhdlout_write_entity = "TRUE"; vhdlout_write_top_configuration = "FALSE"; vhdlout_zero_name = "'0'"; vhdlout_levelize = "FALSE"; vhdlout_dont_create_dummy_nets = "FALSE"; /* variables pertaining to VHDL library generation */ vhdllib_timing_mesg = "true"; vhdllib_timing_xgen = "false"; vhdllib_timing_checks = "true"; vhdllib_negative_constraint = "false"; vhdllib_glitch_handle = "true"; vhdllib_pulse_handle = "use_vhdllib_glitch_handle" vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; vhdllib_tb_compare = 0; vhdllib_tb_x_eq_dontcare = FALSE; vhdllib_logic_system = "ieee-1164"; vhdllib_logical_name = ""; /* variables pertaining to technology library processing */ read_db_lib_warnings = FALSE; read_translate_msff = TRUE; libgen_max_differences = -1; /* View Variable Group: These variables define the behavior of the Design_Analyzer. Each user may wish to customize the cursor color, or , , etc. of the viewer in his/her own .synopsys file. */ view_maximum_route_grids = 0 ; view_dialogs_modal = "true" ; view_disable_error_windows = "false" ; view_error_window_count = 6 ; view_log_file = "" ; view_busy_during_selection = "true" ; view_set_cursor_area = 5 ; view_cache_images = "true" ; view_draw_text_breakpoint = 0.01 ; view_use_integer_scaling = "false" ; view_use_x_routines = "true" ; view_disable_output = "false" ; view_arch_types = {apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc} ; view_icon_path = init_path + "/icons" ; view_background = "black" ; view_disable_cursor_warping = "true" ; view_watcher = bin_path + "/da_watcher_exec" ; view_command_win_max_lines = 1000 ; view_select_separator = " - " ; view_select_default_message = "Left Button: Select - Middle Button: Add/Modify Select - Right Button: Menu" ; view_on_line_doc_cmd = synopsys_root + "/worldview/bin/iview"; view_info_search_cmd = synopsys_root + "/infosearch/scripts/InfoSearch"; view_script_submenu_items = {}; x11_set_cursor_number = -1 ; x11_set_cursor_foreground = "" ; x11_set_cursor_background = "" ; view_set_selecting_color = "" ; view_use_small_cursor = "" ; view_tools_menu_items = {}; /* added for star 12763 */ text_unselect_on_button_press = "true" ; /* affect the HDL Text Viewer */ text_editor_command = "xterm -fn 8x13 -e vi %s &" ; test_design_analyzer_uses_insert_scan = "false" ; /* If you like emacs, uncomment the next line */ /* text_editor_command = "emacs -fn 8x13 %s &" ; */ /* You can delete pairs from this list, but you can't add new ones * unless you also update the UIL files. So, customers can not add * dialogs to this list, only Synopsys can do that. */ view_independent_dialogs = { "test_report", " Test Reports ", \ "report_print", " Report ", \ "report_options", " Report Options ", \ "report_win", " Report Output ", \ "manual_page", " Manual Page " } ; /* if color Silicon Graphics workstation */ if( x11_vendor_string == "Silicon" && x11_is_color == "true") { x11_set_cursor_foreground = "magenta" ; view_use_small_cursor = "true" ; view_set_selecting_color = "white" ; } /* if running on an Apollo machine */ if( x11_vendor_string == "Apollo " || arch == "apollo") { enable_page_mode = "false" ; } else { enable_page_mode = "true" ; } /* don't work around this bug on the Apollo */ if( x11_vendor_string == "Apollo ") { view_extend_thick_lines = "false" ; } \ else { view_extend_thick_lines = "true" ; } /* Suffix Variable Group: Suffixes recognized by the Design Analyzer menu in file choices */ view_read_file_suffix = {db, gdb, sdb, edif, eqn, fnc, lsi, mif, NET, pla, st, tdl, v, vhd, vhdl, xnf} ; view_analyze_file_suffix = {v, vhd, vhdl} ; view_write_file_suffix = {gdb, db, sdb, do, edif, eqn, fnc, lsi, NET, neted, pla, st, tdl, v, vhd, vhdl, xnf} ; view_execute_script_suffix = {.script, .scr, .dcs, .dcv, .dc, .con} ; view_arch_types = {apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc} ; /* links_to_layout Variable Group: These variables affect the read_timing, write_timing set_annotated_delay, compile, and reoptimize_design commands. */ auto_wire_load_selection = "true" ; /* power Variable Group: These variables affect the behavior of power analysis. */ power_keep_license_after_power_commands = "false" /* BC Variable Group: These variables affect the BC behavior */ /* enable chaining and multi-cycle operations */ bc_enable_chaining = "true" bc_enable_multi_cycle = "true" bc_time_all_sequential_op_bindings = "false" bc_enable_speculative_execution = "false" bc_fsm_coding_style = "one_hot" /* Variable Group Definitions: The group_variable() command groups variables for display in the "File/Defaults" dialog and defines groups of variables for the list() command. */ /* "links_to_layout" variables are used by multiple commands */ /* auto_wire_load_selection is also in the "compile" variable group. */ group_variable( links_to_layout, "auto_wire_load_selection"); /* variables starting with "compile" are also in the compile variable group */ group_variable( links_to_layout, "compile_dont_touch_annotated_cell_during_inplace_opt"); group_variable( links_to_layout, "compile_ignore_footprint_during_inplace_opt"); group_variable( links_to_layout, "compile_ignore_area_during_inplace_opt"); group_variable( links_to_layout, "compile_ok_to_buffer_during_inplace_opt"); group_variable( links_to_layout, "compile_disable_area_opt_during_inplace_opt"); group_variable( links_to_layout, "compile_update_annotated_delays_during_inplace_opt"); group_variable( links_to_layout, "reoptimize_design_changed_list_file_name"); group_variable( links_to_layout, "reoptimize_design_disable_area_opt_during_postlayout_opt"); group_variable( links_to_layout, "sdfout_allow_non_positive_constraints"); /* to find the XErrorDB and XKeySymDB for X11 file */ motif_files = synopsys_root + "/admin/setup" ; /* set filename for logging input file */ filename_log_file = "filenames.log" ; /* whether to delete the filename log after the normal exits */ exit_delete_filename_log_file = "true"; /* "system" variables are used by multiple commands */ group_variable( system, "auto_link_disable"); group_variable( system, "auto_link_options"); group_variable( system, "command_log_file"); group_variable( system, "company") ; group_variable( system, "compatibility_version") ; group_variable( system, "current_design") ; group_variable( system, "current_instance"); group_variable( system, "dc_shell_status") ; group_variable( system, "designer") ; group_variable( system, "echo_include_commands") ; group_variable( system, "enable_page_mode") ; group_variable( system, "change_names_update_inst_tree") ; group_variable( system, "change_names_dont_change_bus_members") ; group_variable( system, "default_name_rules") ; group_variable( system, "verbose_messages"); group_variable( system, "link_library") ; group_variable( system, "link_force_case") ; group_variable( system, "search_path") ; group_variable( system, "synthetic_library") ; group_variable( system, "target_library") ; group_variable( system, "uniquify_naming_style") ; group_variable( system, "suppress_errors") ; group_variable( system, "find_converts_name_lists"); group_variable( system, "filename_log_file"); group_variable( system, "exit_delete_filename_log_file"); group_variable( system, "syntax_check_status"); group_variable( system, "context_check_status"); /* "compile" variables are used by the compile command */ group_variable( compile, "compile_assume_fully_decoded_three_state_busses") ; group_variable( compile, "compile_fix_multiple_port_nets") ; group_variable( compile, "compile_no_new_cells_at_top_level") ; group_variable( compile, "compile_preserve_sync_resets") ; group_variable( compile, "compile_ignore_area_during_inplace_opt") ; group_variable( compile, "compile_ignore_footprint_during_inplace_opt") ; group_variable( compile, "compile_dont_touch_annotated_cell_during_inplace_opt") ; group_variable( compile, "compile_ok_to_buffer_during_inplace_opt") ; group_variable( compile, "reoptimize_design_changed_list_file_name"); group_variable( compile, "compile_disable_area_opt_during_inplace_opt"); group_variable( compile, "compile_update_annotated_delays_during_inplace_opt"); group_variable( compile, "compile_instance_name_prefix") ; group_variable( compile, "compile_instance_name_suffix") ; group_variable( compile, "compile_negative_logic_methodology") ; group_variable( compile, "compile_disable_hierarchical_inverter_opt"); group_variable( compile, "port_complement_naming_style") ; group_variable( compile, "auto_wire_load_selection") ; group_variable( compile, "compile_implementation_selection") ; group_variable( compile, "compile_use_fast_delay_mode") ; group_variable( compile, "compile_use_low_timing_effort") ; group_variable( compile, "compile_mux_no_boundary_optimization"); group_variable( compile, "compile_create_mux_op_hierarchy"); group_variable( compile, "compile_preserve_subdesign_interfaces"); group_variable( compile, "actel_seq_opto"); group_variable( compile, "actel_qbar_opto"); /* "synthetic_library" variables */ group_variable( synlib, "synthetic_library") ; group_variable( synlib, "hdlin_replace_synthetic") ; group_variable( synlib, "synlib_dont_get_license") ; group_variable( synlib, "synlib_evaluation_mode") ; group_variable( synlib, "synlib_optimize_non_cache_elements") ; group_variable( synlib, "synlib_model_map_effort") ; group_variable( synlib, "synlib_disable_limited_licenses"); group_variable( synlib, "synlib_sequential_module"); group_variable( synlib, "cache_read") ; group_variable( synlib, "cache_write") ; group_variable( synlib, "cache_read_info") ; group_variable( synlib, "cache_write_info") ; group_variable( synlib, "cache_file_chmod_octal") ; group_variable( synlib, "cache_dir_chmod_octal") ; /* "insert_test" variables are used by the insert_test command */ group_variable( insert_test, "insert_test_design_naming_style") ; /*group_variable( insert_test, "insert_test_scan_chain_only_one_clock"); Replaced by command line option (star 17215) -- Denis Martin. 28-Jan-94*/ group_variable( insert_test, "test_clock_port_naming_style") ; group_variable( insert_test, "test_default_min_fault_coverage"); group_variable( insert_test, "test_scan_clock_a_port_naming_style") ; group_variable( insert_test, "test_scan_clock_b_port_naming_style") ; group_variable( insert_test, "test_scan_clock_port_naming_style") ; group_variable( insert_test, "test_scan_enable_inverted_port_naming_style") ; group_variable( insert_test, "test_scan_enable_port_naming_style") ; group_variable( insert_test, "test_scan_in_port_naming_style") ; group_variable( insert_test, "test_scan_out_port_naming_style") ; group_variable( insert_test, "test_non_scan_clock_port_naming_style"); group_variable( insert_test, "insert_test_map_effort_enabled"); group_variable( insert_test, "test_disable_constraint_smart_insert"); group_variable( insert_test, "test_isolate_hier_scan_out"); /* "preview_scan" variables are used by the preview_scan command */ group_variable( preview_scan, "test_preview_scan_shows_cell_types"); group_variable( preview_scan, "test_scan_link_so_lockup_key"); group_variable( preview_scan, "test_scan_link_wire_key"); group_variable( preview_scan, "test_scan_segment_key"); group_variable( preview_scan, "test_scan_true_key"); /* "testmanager" variables */ group_variable( testmanager, "multi_pass_test_generation") ; /* "testsim" variables */ group_variable( testsim, "testsim_print_stats_file") ; /* "test" variables */ group_variable( test, "test_default_bidir_delay"); group_variable( test, "test_default_delay"); group_variable( test, "test_default_period"); group_variable( test, "test_default_strobe"); group_variable( test, "test_default_strobe_width"); group_variable( test, "test_capture_clock_skew"); group_variable( test, "test_allow_clock_reconvergence"); group_variable( test, "test_default_scan_style"); /* "jtag" variables */ group_variable( jtag, "jtag_manufacturer_id"); group_variable( jtag, "jtag_part_number"); group_variable( jtag, "jtag_port_drive_limit"); group_variable( jtag, "jtag_version_number"); group_variable( jtag, "jtag_test_data_in_port_naming_style"); group_variable( jtag, "jtag_test_data_out_port_naming_style"); group_variable( jtag, "jtag_test_mode_select_port_naming_style"); group_variable( jtag, "jtag_test_clock_port_naming_style"); group_variable( jtag, "jtag_test_reset_port_naming_style"); /* "atpg" variables are used by the create_test_patterns command */ /* from hikari on, the "atpg_keep_faults_data" variable is obselete group_variable( atpg, "atpg_keep_faults_data") ; */ group_variable( atpg, "atpg_test_asynchronous_pins") ; /* "write_test" variables are used by the write_test command */ group_variable( write_test, "write_test_formats"); group_variable( write_test, "write_test_include_scan_cell_info"); group_variable( write_test, "write_test_input_dont_care_value"); group_variable( write_test, "write_test_max_cycles"); group_variable( write_test, "write_test_max_scan_patterns"); group_variable( write_test, "write_test_pattern_set_naming_style"); group_variable( write_test, "write_test_scan_check_file_naming_style"); group_variable( write_test, "write_test_vector_file_naming_style"); /* "schematic" variables are used by the create_schematic command */ group_variable( schematic, "bus_dimension_separator_style") ; group_variable( schematic, "bus_naming_style") ; group_variable( schematic, "bus_range_separator_style") ; group_variable( schematic, "duplicate_ports") ; group_variable( schematic, "generic_symbol_library") ; group_variable( schematic, "gen_max_ports_on_symbol_side") ; group_variable( schematic, "gen_bussing_exact_implicit") ; group_variable( schematic, "gen_cell_pin_name_separator" ) ; group_variable( schematic, "gen_max_compound_name_length" ) ; group_variable( schematic, "single_group_per_sheet") ; group_variable( schematic, "symbol_library") ; group_variable( schematic, "use_port_name_for_oscs") ; group_variable( schematic, "default_schematic_options") ; group_variable( schematic, "gen_match_ripper_wire_widths") ; group_variable( schematic, "gen_show_created_busses") ; group_variable( schematic, "gen_show_created_symbols") ; group_variable( schematic, "gen_dont_show_single_bit_busses") ; group_variable( schematic, "gen_single_osc_per_name") ; group_variable( schematic, "gen_create_netlist_busses") ; group_variable( schematic, "gen_open_name_prefix") ; group_variable( schematic, "gen_open_name_postfix") ; group_variable( schematic, "sort_outputs") ; /* "view" variables are used by the design_analyzer */ group_variable( view, "x11_set_cursor_background") ; group_variable( view, "x11_set_cursor_foreground") ; group_variable( view, "x11_set_cursor_number") ; if (x11_is_color != "x11_is_color") { group_variable( view, "x11_is_color") ; group_variable( view, "x11_display_string") ; group_variable( view, "x11_vendor_version_number") ; group_variable( view, "x11_vendor_release_number") ; group_variable( view, "x11_vendor_string") ; } group_variable( view, "default_schematic_options") ; group_variable( view, "view_arch_types") ; group_variable( view, "view_background") ; group_variable( view, "view_command_log_file") ; group_variable( view, "view_dialogs_modal") ; group_variable( view, "view_disable_cursor_warping") ; group_variable( view, "view_disable_error_windows") ; group_variable( view, "view_error_window_count") ; group_variable( view, "view_log_file") ; group_variable( view, "view_use_x_routines") ; group_variable( view, "view_cache_images") ; group_variable( view, "view_disable_output") ; group_variable( view, "view_command_win_max_lines") ; group_variable( view, "view_on_line_doc_cmd") ; group_variable( view, "view_info_search_cmd") ; group_variable( view, "view_script_submenu_items") ; group_variable( view, "view_use_small_cursor" ); /* These next variable are also in the `suffix' group */ group_variable( view, "view_execute_script_suffix") ; group_variable( view, "view_read_file_suffix") ; group_variable( view, "view_analyze_file_suffix") ; group_variable( view, "view_write_file_suffix") ; /* group the text viewer variable with the other Design Analyzer variables. */ group_variable( view, "text_editor_command" ); group_variable( view, "text_print_command") ; group_variable( view, "view_use_small_cursor" ); group_variable( view, "view_tools_menu_items"); group_variable( view, "test_design_analyzer_uses_insert_scan"); /* "io" variables are used by the read, read_lib, db2sge and write commands */ group_variable( io, "bus_inference_descending_sort") ; group_variable( io, "bus_inference_style") ; group_variable( io, "db2sge_output_directory"); group_variable( io, "db2sge_scale"); group_variable( io, "db2sge_overwrite"); group_variable( io, "db2sge_display_symbol_names"); group_variable( io, "db2sge_display_pin_names"); group_variable( io, "db2sge_display_instance_names"); group_variable( io, "db2sge_use_bustaps"); group_variable( io, "db2sge_use_compound_names"); group_variable( io, "db2sge_bit_type"); group_variable( io, "db2sge_bit_vector_type"); group_variable( io, "db2sge_one_name"); group_variable( io, "db2sge_zero_name"); group_variable( io, "db2sge_unknown_name"); group_variable( io, "db2sge_target_xp"); group_variable( io, "db2sge_tcf_package_file"); group_variable( io, "db2sge_use_lib_section"); group_variable( io, "db2sge_script") ; group_variable( io, "db2sge_command") ; group_variable( io, "equationout_and_sign") ; group_variable( io, "equationout_or_sign") ; group_variable( io, "equationout_postfix_negation") ; group_variable( io, "lsiin_net_name_prefix") ; group_variable( io, "lsiout_inverter_cell") ; group_variable( io, "lsiout_upcase") ; group_variable( io, "mentor_bidirect_value") ; group_variable( io, "mentor_do_path") ; group_variable( io, "mentor_input_output_property_name") ; group_variable( io, "mentor_input_value") ; group_variable( io, "mentor_logic_one_value") ; group_variable( io, "mentor_logic_zero_one_property_name") ; group_variable( io, "mentor_logic_zero_value") ; group_variable( io, "mentor_output_value") ; group_variable( io, "mentor_primitive_property_name") ; group_variable( io, "mentor_primitive_property_value") ; group_variable( io, "mentor_reference_property_name") ; group_variable( io, "mentor_search_path") ; group_variable( io, "mentor_write_symbols") ; group_variable( io, "pla_read_create_flip_flop") ; group_variable( io, "tdlout_upcase") ; group_variable( io, "write_name_nets_same_as_ports") ; group_variable( io, "xnfout_constraints_per_endpoint") ; group_variable( io, "xnfout_default_time_constraints") ; group_variable( io, "xnfout_clock_attribute_style") ; group_variable( io, "xnfout_library_version") ; group_variable( io, "xnfin_family") ; group_variable( io, "xnfin_ignore_pins") ; group_variable( io, "xnfin_dff_reset_pin_name") ; group_variable( io, "xnfin_dff_set_pin_name") ; group_variable( io, "xnfin_dff_clock_enable_pin_name") ; group_variable( io, "xnfin_dff_data_pin_name") ; group_variable( io, "xnfin_dff_clock_pin_name") ; group_variable( io, "xnfin_dff_q_pin_name"); group_variable( io, "sdfin_min_rise_net_delay"); group_variable( io, "sdfin_min_fall_net_delay"); group_variable( io, "sdfin_min_rise_cell_delay"); group_variable( io, "sdfin_min_fall_cell_delay"); group_variable( io, "sdfin_rise_net_delay_type"); group_variable( io, "sdfin_fall_net_delay_type"); group_variable( io, "sdfin_rise_cell_delay_type"); group_variable( io, "sdfin_fall_cell_delay_type"); group_variable( io, "sdfin_top_instance_name"); group_variable( io, "sdfout_time_scale"); group_variable( io, "sdfout_write_to_output"); group_variable( io, "sdfout_top_instance_name"); group_variable( io, "sdfout_min_rise_net_delay"); group_variable( io, "sdfout_min_fall_net_delay"); group_variable( io, "sdfout_min_rise_cell_delay"); group_variable( io, "sdfout_min_fall_cell_delay"); group_variable( io, "read_db_lib_warnings"); group_variable( io, "read_translate_msff"); group_variable( io, "libgen_max_differences"); group_variable( io,"read_name_mapping_nowarn_libraries") ; group_variable( io,"write_name_mapping_nowarn_libraries") ; /* "edif" variables are used by the EDIF format read, read_lib, write, and write_lib commands */ group_variable( edif, "bus_dimension_separator_style") ; group_variable( edif, "bus_extraction_style") ; group_variable( edif, "bus_inference_descending_sort") ; group_variable( edif, "bus_inference_style") ; group_variable( edif, "bus_naming_style") ; group_variable( edif, "bus_range_separator_style") ; group_variable( edif, "edifin_autoconnect_offpageconnectors") ; group_variable( edif, "edifin_autoconnect_ports") ; group_variable( edif, "edifin_delete_empty_cells") ; group_variable( edif, "edifin_delete_ripper_cells") ; group_variable( edif, "edifin_ground_net_name") ; group_variable( edif, "edifin_ground_net_property_name") ; group_variable( edif, "edifin_ground_net_property_value") ; group_variable( edif, "edifin_ground_port_name") ; group_variable( edif, "edifin_instance_property_name") ; group_variable( edif, "edifin_portinstance_disabled_property_name") ; group_variable( edif, "edifin_portinstance_disabled_property_value") ; group_variable( edif, "edifin_portinstance_property_name") ; group_variable( edif, "edifin_power_net_name") ; group_variable( edif, "edifin_power_net_property_name") ; group_variable( edif, "edifin_power_net_property_value") ; group_variable( edif, "edifin_power_port_name") ; group_variable( edif, "edifin_use_identifier_in_rename") ; group_variable( edif, "edifin_view_identifier_property_name") ; group_variable( edif, "edifin_dc_script_flag") ; group_variable( edif, "edifin_lib_logic_1_symbol") ; group_variable( edif, "edifin_lib_logic_0_symbol") ; group_variable( edif, "edifin_lib_in_port_symbol") ; group_variable( edif, "edifin_lib_out_port_symbol") ; group_variable( edif, "edifin_lib_inout_port_symbol") ; group_variable( edif, "edifin_lib_in_osc_symbol") ; group_variable( edif, "edifin_lib_out_osc_symbol") ; group_variable( edif, "edifin_lib_inout_osc_symbol") ; group_variable( edif, "edifin_lib_mentor_netcon_symbol") ; group_variable( edif, "edifin_lib_ripper_bits_property") ; group_variable( edif, "edifin_lib_ripper_bus_end") ; group_variable( edif, "edifin_lib_ripper_cell_name") ; group_variable( edif, "edifin_lib_ripper_view_name") ; group_variable( edif, "edifin_lib_route_grid") ; group_variable( edif, "edifin_lib_templates") ; group_variable( edif, "edifout_dc_script_flag") ; group_variable( edif, "edifout_design_name") ; group_variable( edif, "edifout_designs_library_name") ; group_variable( edif, "edifout_display_instance_names") ; group_variable( edif, "edifout_display_net_names") ; group_variable( edif, "edifout_external") ; group_variable( edif, "edifout_external_graphic_view_name") ; group_variable( edif, "edifout_external_netlist_view_name") ; group_variable( edif, "edifout_external_schematic_view_name") ; group_variable( edif, "edifout_ground_name") ; group_variable( edif, "edifout_ground_net_name") ; group_variable( edif, "edifout_ground_net_property_name") ; group_variable( edif, "edifout_ground_net_property_value") ; group_variable( edif, "edifout_ground_pin_name") ; group_variable( edif, "edifout_ground_port_name") ; group_variable( edif, "edifout_instance_property_name") ; group_variable( edif, "edifout_instantiate_ports") ; group_variable( edif, "edifout_library_graphic_view_name") ; group_variable( edif, "edifout_library_netlist_view_name") ; group_variable( edif, "edifout_library_schematic_view_name") ; group_variable( edif, "edifout_merge_libraries") ; group_variable( edif, "edifout_multidimension_arrays") ; group_variable( edif, "edifout_name_oscs_different_from_ports") ; group_variable( edif, "edifout_name_rippers_same_as_wires") ; group_variable( edif, "edifout_netlist_only") ; group_variable( edif, "edifout_no_array") ; group_variable( edif, "edifout_numerical_array_members") ; group_variable( edif, "edifout_pin_direction_property_name") ; group_variable( edif, "edifout_pin_direction_in_value") ; group_variable( edif, "edifout_pin_direction_inout_value") ; group_variable( edif, "edifout_pin_direction_out_value") ; group_variable( edif, "edifout_pin_name_property_name") ; group_variable( edif, "edifout_portinstance_disabled_property_name") ; group_variable( edif, "edifout_portinstance_disabled_property_value") ; group_variable( edif, "edifout_portinstance_property_name") ; group_variable( edif, "edifout_power_and_ground_representation") ; group_variable( edif, "edifout_power_name") ; group_variable( edif, "edifout_power_net_name") ; group_variable( edif, "edifout_power_net_property_name") ; group_variable( edif, "edifout_power_net_property_value") ; group_variable( edif, "edifout_power_pin_name") ; group_variable( edif, "edifout_power_port_name") ; group_variable( edif, "edifout_skip_port_implementations") ; group_variable( edif, "edifout_target_system") ; group_variable( edif, "edifout_top_level_symbol") ; group_variable( edif, "edifout_translate_origin") ; group_variable( edif, "edifout_unused_property_value") ; group_variable( edif, "edifout_write_attributes") ; group_variable( edif, "edifout_write_constraints") ; group_variable( edif, "edifout_write_properties_list") ; group_variable( edif, "write_name_nets_same_as_ports") ; /* "hdl" variables are variables pertaining to hdl reading and optimizing */ group_variable( hdl, "bus_dimension_separator_style") ; group_variable( hdl, "bus_minus_style") ; group_variable( hdl, "bus_naming_style") ; group_variable( hdl, "design_library_file") ; group_variable( hdl, "hdlin_advisor_directory"); group_variable( hdl, "hdlin_hide_resource_line_numbers"); group_variable( hdl, "hdlin_auto_save_templates") ; group_variable( hdl, "hdlin_replace_synthetic") ; group_variable( hdl, "hdlin_latch_always_async_set_reset") ; group_variable( hdl, "hdlin_ff_always_sync_set_reset") ; group_variable( hdl, "hdlin_ff_always_async_set_reset") ; group_variable( hdl, "hdlin_keep_feedback") ; group_variable( hdl, "hdlin_keep_inv_feedback") ; group_variable( hdl, "hdlin_check_no_latch") ; group_variable( hdl, "hdlin_report_inferred_modules") ; group_variable( hdl, "hdlin_reg_report_length") ; group_variable( hdl, "hdlin_translate_off_skip_text") ; group_variable( hdl, "hdlin_infer_mux") ; group_variable( hdl, "hdlin_dont_infer_mux_for_resource_sharing") ; group_variable( hdl, "hdlin_mux_size_limit") ; group_variable( hdl, "hdl_preferred_license") ; group_variable( hdl, "hdl_keep_licenses") ; group_variable( hdl, "hlo_resource_allocation") ; group_variable( hdl, "hlo_transform_constant_multiplication") ; group_variable( hdl, "hlo_minimize_tree_delay" ) ; group_variable( hdl, "hlo_resource_implementation" ) ; group_variable( hdl, "hlo_share_common_subexpressions" ) ; group_variable( hdl, "hlo_share_effort" ) ; group_variable( hdl, "hlo_ignore_priorities" ) ; group_variable( hdl, "hdl_naming_threshold") ; group_variable( hdl, "template_naming_style") ; group_variable( hdl, "template_parameter_style") ; group_variable( hdl, "template_separator_style") ; group_variable( hdl, "verilogout_equation") ; group_variable( hdl, "verilogout_ignore_case") ; group_variable( hdl, "verilogout_no_tri") ; group_variable( hdl, "verilogout_single_bit") ; group_variable( hdl, "verilogout_higher_designs_first") ; group_variable( hdl, "verilogout_levelize") ; group_variable( hdl, "verilogout_include_files") ; group_variable( hdl, "verilogout_unconnected_prefix") ; group_variable( hdl, "verilogout_show_unconnected_pins") ; /* "vhdlio" variables are variables pertaining to VHDL generation */ group_variable( vhdlio, "vhdllib_timing_mesg") ; group_variable( vhdlio, "vhdllib_timing_xgen") ; group_variable( vhdlio, "vhdllib_timing_checks") ; group_variable( vhdlio, "vhdllib_negative_constraint") ; group_variable( vhdlio, "vhdllib_pulse_handle") ; group_variable( vhdlio, "vhdllib_glitch_handle") ; group_variable( vhdlio, "vhdllib_architecture") ; group_variable( vhdlio, "vhdllib_tb_compare") ; group_variable( vhdlio, "vhdllib_tb_x_eq_dontcare") ; group_variable( vhdlio, "vhdllib_logic_system") ; group_variable( vhdlio, "vhdllib_logical_name") ; group_variable( vhdlio, "vhdlout_architecture_name") ; group_variable( vhdlio, "vhdlout_bit_type") ; group_variable( vhdlio, "vhdlout_bit_type_resolved") ; group_variable( vhdlio, "vhdlout_bit_vector_type") ; group_variable( vhdlio, "vhdlout_conversion_functions" ); group_variable( vhdlio, "vhdlout_dont_write_types") ; group_variable( vhdlio, "vhdlout_equations") ; group_variable( vhdlio, "vhdlout_one_name") ; group_variable( vhdlio, "vhdlout_package_naming_style" ); group_variable( vhdlio, "vhdlout_preserve_hierarchical_types" ); group_variable( vhdlio, "vhdlout_separate_scan_in") ; group_variable( vhdlio, "vhdlout_single_bit") ; group_variable( vhdlio, "vhdlout_target_simulator") ; group_variable( vhdlio, "vhdlout_top_configuration_arch_name") ; group_variable( vhdlio, "vhdlout_top_configuration_entity_name") ; group_variable( vhdlio, "vhdlout_top_configuration_name") ; group_variable( vhdlio, "vhdlout_three_state_name") ; group_variable( vhdlio, "vhdlout_three_state_res_func") ; group_variable( vhdlio, "vhdlout_time_scale") ; group_variable( vhdlio, "vhdlout_unknown_name") ; group_variable( vhdlio, "vhdlout_use_packages") ; group_variable( vhdlio, "vhdlout_wired_and_res_func") ; group_variable( vhdlio, "vhdlout_wired_or_res_func") ; group_variable( vhdlio, "vhdlout_write_architecture") ; group_variable( vhdlio, "vhdlout_write_entity") ; group_variable( vhdlio, "vhdlout_write_top_configuration") ; group_variable( vhdlio, "vhdlout_write_components" ); group_variable( vhdlio, "vhdlout_zero_name") ; group_variable( vhdlio, "vhdlout_levelize") ; group_variable( vhdlio, "vhdlout_dont_create_dummy_nets") ; /* "plot" variables are used by the plot command and by * the plotting function in the schematic viewer */ group_variable( plot, "plot_box") ; group_variable( plot, "plot_command") ; group_variable( plot, "plot_orientation") ; group_variable( plot, "plot_scale_factor") ; group_variable( plot, "plotter_maxx") ; group_variable( plot, "plotter_maxy") ; group_variable( plot, "plotter_minx") ; group_variable( plot, "plotter_miny") ; /* "suffix" variables are used to find the suffixes of different file types */ group_variable( suffix, "view_execute_script_suffix") ; group_variable( suffix, "view_read_file_suffix") ; group_variable( suffix, "view_analyze_file_suffix") ; group_variable( suffix, "view_write_file_suffix") ; /* "bc" variables are used by BC to control scheduling behavior */ group_variable( bc, "bc_enable_chaining"); group_variable( bc, "bc_enable_multi_cycle"); group_variable( bc, "bc_time_all_sequential_op_bindings"); group_variable( bc, "bc_enable_speculative_execution"); group_variable( bc, "bc_fsm_coding_style"); /* "power" variables are for power-analysis. */ group_variable( power, "power_keep_license_after_power_commands"); /* Aliases for backwards compatibility or other reasons */ alias view_cursor_number x11_set_cursor_number alias set_internal_load set_load alias set_internal_arrival set_arrival alias set_connect_delay "set_annotated_delay -net" alias create_test_vectors create_test_patterns alias compile_test insert_test alias man help alias check_clocks check_timing alias lint check_design alias verify compare_design alias gen create_schematic alias free remove_design alias group_bus create_bus alias ungroup_bus remove_bus alias groupvar group_variable alias report_constraints report_constraint alias report_attributes report_attribute alias fsm_reduce reduce_fsm alias fsm_minimize minimize_fsm alias disable_timing set_disable_timing alias dont_touch set_dont_touch alias dont_touch_network set_dont_touch_network alias dont_use set_dont_use alias fix_hold set_fix_hold alias prefer set_prefer alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" alias analyze_scan preview_scan /* The ls command is gone, now it is just an alias */ if( arch == "mips" && \ ( synopsys_program_name == "design_analyzer" || isatty == 0)) { alias ls sh ls -a } \ else if(( arch == "mips") || ( arch == "necmips" )) { alias ls sh ls -aC } \ else { alias ls sh ls -aC } /* Aliases added for report command */ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" alias report_clock_tree "report_transitive_fanout -clock_tree" alias report_clocks report_clock alias report_register "report_timing_requirements;report_clock -skew" alias report_synthetic report_cell /* alias for write_sge and menu item in DA for db2sge */ db2sge_script = synopsys_root + "/admin/setup/.dc_write_sge" ; alias write_sge "include db2sge_script" ; db2sge_command = synopsys_root + "/" + arch + "/syn/bin/db2sge" ; view_script_submenu_items = {"DA to SGE Transfer", "write_sge"} /* read schematic annotation setup file */ include synopsys_root + "/admin/setup/.dc_annotate" /* setup the default layer settings */ include synopsys_root + "/admin/setup/.dc_layers" /* read name rules definition file */ include synopsys_root + "/admin/setup/.dc_name_rules" if (dc_shell_status != 1) { sh echo "Fatal: System .synopsys_dc.setup file not read properly. Please re-invoke." quit }