----------------------------------------------------------------
-- Rebuild the 4-bit latch using structural description using 
-- named signal association. Use latch as the building 
-- component. Use architecture configurations.
----------------------------------------------------------------

ENTITY latch4 IS
  PORT( d: IN bit_vector(3 DOWNTO 0); 
        en,clk: IN bit;
        q: OUT bit_vector(3 DOWNTO 0));
END ENTITY latch4;

ARCHITECTURE struct OF latch4 IS
  COMPONENT latch
    PORT( d, clk: IN bit; 
          q, nq: OUT bit);
  END COMPONENT latch;

  COMPONENT and2
    PORT( a, b: IN bit; c: OUT bit);
  END COMPONENT and2;

  FOR ALL: latch USE ENTITY WORK.latch(behav);
  FOR gate: and2 USE ENTITY WORK.and2(and2);

  SIGNAL int_clk: bit;
BEGIN
  bit3:  latch
    PORT MAP (d =>d(3), clk => int_clk, q => q(3), qn => open);
  bit2:  latch
    PORT MAP (clk => int_clk, d => d(2), q => q(2));
  bit1:  latch
    PORT MAP (q => q(1), d => d(1), clk => int_clk);
  bit0:  latch
    PORT MAP (d => d(0), q => q(0), clk => int_clk);
  gate:  and2
    PORT MAP (a => en, b => clk, c => int_clk);
END ARCHITECTURE struct;