-------------------------------------------
-- A ROM to build a squaring circuit. 
-------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL; -- for the conv_integer function

ENTITY rom IS
  GENERIC(      n : integer := 3;
        m : integer := 6);
  PORT(    addr: IN std_logic_vector(n-1 DOWNTO 0);
      enable: IN bit;
      data: OUT std_logic_vector (m-1 DOWNTO 0));
END ENTITY rom;

------------------------------------------------------------------
-- Use a flag to ensure that the ROM is initialize only one time
------------------------------------------------------------------

ARCHITECTURE flag_arch OF rom IS
  TYPE rm IS ARRAY (0 TO 2**n-1) OF std_logic_vector (m-1 DOWNTO 0);
  SIGNAL word: rm;
  SIGNAL initialized: boolean := false;
BEGIN
  memory: PROCESS (enable, addr) IS 
  
  BEGIN
    IF NOT initialized THEN
      FOR index IN word'range LOOP
        word(index) <= conv_std_logic_vector(index*index,m);
      END LOOP;
      initialized <= true;
    END IF;
    IF enable = '1' THEN
      data <= word(conv_integer(addr));
    ELSE 
      data <= (OTHERS => 'Z');
    END IF;
  END PROCESS memory;
END ARCHITECTURE flag_arch;


-----------------------------
-- Using a LOOP statement
-----------------------------

ARCHITECTURE loop_arch OF rom IS
  TYPE rm IS ARRAY (0 TO 2**n-1) OF std_logic_vector (m-1 DOWNTO 0);
  SIGNAL word: rm;
BEGIN
  memory: PROCESS (enable, addr) IS 
  BEGIN
    FOR index IN word'range LOOP
      word(index) <= conv_std_logic_vector(index*index,m);
    END LOOP;
    LOOP
      WAIT ON enable, addr;
      IF enable = '1' THEN
        data <= word(conv_integer(addr));
      ELSE 
        data <= (OTHERS => 'Z');
      END IF;
    END LOOP;
  END PROCESS memory;
END ARCHITECTURE loop_arch;
end{tabbing}
}

----------------------------------------------------
--- Using a separate process to initialize the ROM
----------------------------------------------------

ARCHITECTURE waiting_process_arch OF rom IS
  TYPE rm IS ARRAY (0 TO 2**n-1) OF std_logic_vector (m-1 DOWNTO 0);
  SIGNAL word: rm;
  SIGNAL initialized: boolean := false;
BEGIN
  init: PROCESS IS
  BEGIN
    FOR index IN word'range LOOP
      word(index) <= conv_std_logic_vector(index*index,m);
    END LOOP;
    initialized <= true;
    WAIT;
  END PROCESS init;
  memory: PROCESS (initialized, enable, addr) IS
  BEGIN
    IF initialized THEN
      IF enable = '1' THEN
        data <= word(conv_integer(addr));
      ELSE 
        data <= (OTHERS => 'Z');
      END IF;
    END IF;
  END PROCESS memory;
END ARCHITECTURE waiting_process_arch;

-------------------------------------------
--- Initializing the ROM with a function.
-------------------------------------------

ARCHITECTURE function_arch OF rom IS
  TYPE rm IS ARRAY (0 TO 2**n-1) OF std_logic_vector (m-1 DOWNTO 0);
  FUNCTION rom_fill RETURN rm IS
    VARIABLE memory: rm;
  BEGIN
    FOR index IN memory'range LOOP
      memory(index) <= conv_std_logic_vector(index*index,m);
    END LOOP;
    RETURN memory;
  END FUNCTION rom_fill;
  constant word: rm := rom_fill;
BEGIN
  memory: PROCESS (enable, addr) IS BEGIN
    IF enable = '1' THEN
      data <= word(conv_integer(addr));
    ELSE 
      data <= (OTHERS => 'Z');
    END IF;
  END PROCESS memory;
END ARCHITECTURE function_arch;

------------------------------------------
-- Initializing the ROM from a text file
------------------------------------------

USE std.textio.ALL;

  FUNCTION rom_fill RETURN rm IS
    VARIABLE memory: rm;
    FILE f: text OPEN READ_MODE IS "rom.txt";
    VARIABLE l: line;
  BEGIN
    FOR index IN memory'range LOOP
      readline (f, l);
      read (l, memory(index));
    END LOOP;
    RETURN memory;
  END FUNCTION rom_fill;