Computer Engineering 465 / Electrical Engineering 543
DIGITAL VLSI
SYSTEMS
Getting Acquainted with
Synopsys
Sample Project
This lab is to be carried out before you start your projects. You are
not required to design any system in this lab. Everything is given to
you.
You are required only to follow the Synopsys tutorial given in the Synopsys
introduction page and apply the steps to the provided sample
project,
given below. It is recommended that you go through all the steps from
the
beginning to the end.
Objectives
Introducing the VHDL project work methodology.
Preparing the directory hierarchy for the projects
Giving you a template for writing your projects.
Getting more familiar with Synopsys kit and its software tools.
Sample
Project
This is a simple project of using a VHDL behavioral description of a
component
and another VHDL file to instantiate this component in building another
system.
In this example, we will design an "equality-check" circuit. The
circuit
takes two 1-bit inputs and gives an output of '1' in case they are
equal
and '0' otherwise. We will build this circuit by instantiating a
"subtraction
circuit". Normally, such projects are split in two (or more) files:
- Low-level
component file. This file includes the component entity
declaration,
its architecture and the package declaration for a VHDL behavioral
description
of a simple "subtraction" circuit. The package declaration will allow
using
the component in more complicated designs.
- Top-level
description file. This file describes the top-level that
instantiates
the simple "subtraction" circuit in a VHDL description of an
"equality-check"
circuit. This files uses the low-level component and connects it with
the
appropriate internal signals.
- Simulation
command file. This file holds simulation commands to cause
the
traced signals to be listed in a waveform window. It also assigns a
stimulus
to signals input and instructs the simulator to run for specific time
periods.
- Testbench
file. This file includes a VHDL description of the equal
circuit
stimuli and corresponding expected outputs that verify the behavior of
it over time. This files uses the top-level component and connects it
with
the appropriate internal signals. The simulation commands to cause the
traced signals to be listed in a waveform window is provided in the testbench
command file.
You need to spend some time to understand the details of this design.
