Date Notes

Sessions

 Expected Topics to be Covered
Sept. 7/11
introduction
network review
 Introduction and review of networking concepts
Sept. 11/14/18
 1.1-1.23 [notes]
Review of probability theory, random variables, CDF, PDF, PMF, and some common distributions
Sept. 21
 1.24-1.30, 2.1-2.4 Discrete RVs, Random processes, Markov processes
Sept. 25
 3.1-3.5 [notes]
Markov chains
Sept. 28
 3.6-3.13 Markov matrices

Assignment 1
 Assignment 1 due date: Oct. 5

For all students: Email me your selected topic(s), on/before Nov. 1.
Oct. 5
 4.1-4.12  [notes]
Steady state analysis of Markov chains
Steady state analysis using difference equations.
Google page rank.

Solution: assignment 1
 Course presentation topics
Course presentation logistics
Oct. 12
No lecture today. Move to Dec. 4 for FUN Workshop.
Oct. 16/19
 7.1-7.6 [notes]
Queuing analysis, M/M/1, M/M/1/B queues

Assignment 2 Due date: Oct. 26

Solution: assignment 2
Oct. 23/26
 8.1, 8.2, 8.3 [notes]
 Leaky bucket and token bucket
Oct. 30
Midterm Exam (during lecture time)
[Previous Sample Exam]
Nov. 2/6
9.1-9.4 [notes] Error Control Protocols, SW ARQ, GBN ARQ, SR ARQ
Nov. 9
10.1-10.4 [notes] MAC Protocols, Pure ALOHA, Slotted ALOHA, Stability issue of ALOHA
Nov. 16
 10.5, 10.6  [notes] CSMA/CD, CSMA/CA

Assignment 3
 Due date: Nov. 23

Solution: assignment 3
Nov. 20
  notes   
IEEE 802.11
Nov. 20/23
 11.1, 11.2 [notes]
[Sample Questions] 		Modeling Network Traffic, Poisson Process
Nov. 23
 11.3, 11.5-11.8, 11.12, 11.13 Realistic models for Poisson traffic, Self-similar traffic, On-Off source/ Transmission error model
Nov. 27
 Modeling TCP
Nov. 30
 Review and Q & A

Assignment 4 Due date: Dec. 4

Solution: assignment 4



Dec. 4
    

FUN Workshop, 2:30-5:20pm, in ECS660  

Workshop Schedule
Presentation Videos (TBD)

Dec. 15, 4pm
ELCE 514 Project report due
 
 Final Exam: TBD


Course Info:  Info. from Sample chapters of the textbook can be downloaded from Springer: http://www.springerlink.com/content/978-0-387-74436-0 and the matlab code can be downloaded from Dr. Gebali's website: http://www.ece.uvic.ca/~fayez/book_networking/matlab/
Another reference book "Dimitri Bertsekas and Robert Gallager, Data Networks, Prentice Hall, Second Edition, 1992" can be downloaded at http://web.mit.edu/dimitrib/www/datanets.html

Book helps to review probability:
Introduction to Probability Models, (0125980620), Sheldon M. Ross
http://search.barnesandnoble.com/Introduction-to-Probability-Models/Sheldon-M-Ross/e/9780125980623
http://www.ebook3000.com/Introduction-to-Probability-Models--Ninth-Edition_21843.html

NSERC USRA:
Value of the award is $4500. Faculty members are required to supplement the award by at least 25%. Normal duration of the award is 16 consecutive weeks on a full-time basis.

Please see the attached document from the Office of Research Services and
visit http://www.nserc-crsng.gc.ca/Students-Etudiants/UG-PC/USRA-BRPC_eng.asp
[www.nserc-crsng.gc.ca] for application forms (Form 202) and additional information.

The student will need to:

1. Log onto or Register as a new User on the NSERC site
(http://www.nserc-crsng.gc.ca/OnlineServices-ServicesEnLigne/Index_eng.asp [www.nserc-crsng.gc.ca]).
2. Complete Form 202 Part I online. If you have completed this form online previously, you will
able to update the form. You may not create multiple versions of this form.
3. Print out a copy of the completed application and sign IN BLUE INK where indicated and attach
a copy of official transcripts from all post-secondary institutions EXCEPT UVic. Submit to potential supervisor.
4. Provide the reference number generated by NSERC's online system to your potential supervisor so the supervisor can complete Form 202 Part II.

Career News: http://www.acm.org/membership/careernews/archives/v6_i2#2


Tech News:  Intel HexaCore Processors:
http://hothardware.com/News/Intel-Details-Upcoming-Mobile-HexaCore-Processors/
Chief among these are the company's ongoing research into so-called "digital intelligence," high-speed point-to-point interconnects, and reconfigurable computing. Intel will also give more details on a 48-core single-chip processor it unveiled last December. One of the features the company will discuss is the chip's use of so-called circuit switching rather than packet switching when passing messages. By mapping out the route from core to core before actually sending a message, Intel claims it can vastly accelerate the speed at which information is passed within the chip structure.

Probability problems
  • Secretary_problem: http://en.wikipedia.org/wiki/Secretary_problem
  • The Monty Hall problem can be solved using Bayes' theorem: see http://en.wikipedia.org/wiki/Monty_Hall_problem
  • Dollar cost averaging, myth or fact? http://panlab.cs.uvic.ca/blog/2011/01/17/dollar-cost-averaging-myth-or-fact/

Hands-on book and simulation tool
    - Maria Luisa Merani, Maurizio Casoni, and Walter Cerrroni, Hands-on networking, from theory to practice
    https://www.amazon.com/Hands-Networking-Maria-Luisa-Merani/dp/0521869854
    - ns-3 Tutorial: https://www.nsnam.org/docs/tutorial/html/
    - ns-2 Tutorial: http://www.isi.edu/nsnam/ns/tutorial/