Computer Engineering 465 / Electrical Engineering 543

DIGITAL VLSI SYSTEMS

Graduate Projects

Note: This page includes information for only graduate students taking ELEC 543 pertaining to the project they do for the course.

Project Schedule

Milestone

Date

Task

Task credit: (% of the total project grade)
M1
Wednesday 1 June 2005
 Project selection
 --
M2
Wednesday 15 June 2005
 Project proposal
 10%
M3
Wednesday 13 July 2005
 Project progress report
 15%
M4
Mondday 8 August, 2005
 Project final report
 75%

Project Selection

Each graduate student is required to complete a project to demonstrate some of the following skills:

Generally, projects should be dealing with system design or hardware design of algorithms for communications, DSP, computer arithmetic, security, etc. To get an idea about what students did in the past, a sample of past projects can be found at the bottom of this page.

Before writing the project proposal, send an email to the course account with your project title and topic. I will shortly reply to you with an approval, disapproval, or a request for more information for clarification. This way you can hand in a well-thought project topic.

Your selection email should be sent from a UVic account with your name and student number. It should be short and to the point, including:
  1. Project title
  2. Project topic in one or at most two paragraphs
  3. Project scope (simulation, synthesis, FPGA prototyping, etc.)

Project Proposal

The first credited task to do in the project is the proposal. Your proposal should be clear and complete enough to help me understand what you are targeting. Your well-written proposal should include, but not limited to, the following items:
  1. Front page including: Project title, course number and name, label for which mile stone is that, student name, date of submission.
  2. Project description supported with neat diagrams and citations for references used.
  3. A list of goals to achieve.
  4. A list of tools that would be used.
  5. Activity chart including specific deliverables.
  6. List of references.

Project Progress Report

This mid-way report aims at checking your progress in the project and you are on the right track. At this stage, you are allowed to do minor modifications to what you proposed to fine tune your project. However, you are not allowed to change your project topic completely. Your well-written progress report should include:
  1. Front page that includes: Project title, course number and name, label for which mile stone is that, student name, date of submission. project title.
  2. Abstract and introduction.
  3. Critical literature survey, highlighting similar projects.
  4. A list of goals to achieve
  5. Detailed description of project to design. You should clearly state project specification.
  6. System design supported with neat diagrams
  7. Design methodology with a list of tools to use
  8. Activity chart including specific deliverables
  9. List of references

Project Final Report

The final project report must be complete enough for the reader to understand, compile, and simulate your system without consulting other references. Your well-typed report should include at least the following items (information provided for each item must be concise):
  1. Precise project title
  2. Abstract and introduction
  3. Extensive literature survey, highlighting similar projects.
  4. A project feature list   
  5. Problem description. State objectives and detailed description and specification of the project.
  6. Design solution. Explain your design methodology. This should include design steps, project partitioning, special techniques, programming tricks, etc. Identify the low-level components and the method of instantiating them to build a top-level description. For example, explain the type of the architecture selected (behavioral, dataflow, or structural) and justify your choice. If you are using a behavioral description, state the number of processes used and the function of each one.
  7. Structural diagrams. Identify the project modules according to your modeling. For each module draw an icon showing all input and output signals. Also, show connections between modules. Summarize signal information in the form of a table. For each signal, show its name, mode, type, and any other comments. In addition, any relevant timing diagrams necessary to understand your lab should be carefully drawn.
  8. VHDL source code listing. All source code must be fully documented. Please follow the code style guidelines included in lab web pages.
  9. Test procedure. Clearly explain your test strategy to ensure the correctness of the model. (Remember that designing testbenches is an integral part of the project.) Describe in detail the steps executed by the used testbenches. Justify these steps and show that the selected signal values are sufficient for testing your design. Turn in all code used for testing and include any script either entered directly from the main simulator window or saved in a command file.
  10. Simulation snapshots. Snapshots from your simulation (test case) output should be included in the report. You can include more than one test case in a single screen snapshot. You might want to annotate the simulation snapshots with any relevant comments. Manual annotations are acceptable. Different ways for taking simulation snapshots are included in the tools web page.
  11. Other information. If you are doing a synthesis or downloading your design to an FPGA, add information about that here.
  12. Results and discussion. Briefly comment on your design and its relation to the stated specifications. Summarize errors, pitfalls, and problems encountered while doing the project. Mention new things learned from the project.
  13. References.

Please go through the following checklist before submitting the report:

   
Identify objectives in the problem description

Clear descriptions

Conclusions are suitable for work presented

Length of the report is appropriate

Check spelling and grammar

Proof read the report

Use proper technical writing style

References conform to the IEEE style

Give proper citations to all works used including figures, tables, formulas, etc.

Sample Projects

Project title

Author

Year
A simple enhanced TDM multiplexer R.K. Watson 1999
High speed timing recovery circuit Prasad Sristi 1999
VHDL implementation and simulation of Delaunay triangulation in the plane Debasish Sasmal 1999
A study of CMOS circuit design techniques for low-power high-speed digital VLSI circuits Jasbir Sarao 1999
VLSI implementation of linear phase FIR filter Manjinder Mann 1999
Verification study of the selective cell discarding scheme over ATM networks Omar Mohamed 1999
VHDL modeling of fault tolerant interconnection networks Anjum Shaikh 1999
Issues in FPGA implementation of DSP algorithms A. Gendel 1999
Simulation and modification of Wallace tree digital multipliers J. Kanade 1998
Answering machine controller in VHDL Ashraf Hafez 1997
VLSI design for block matching algorithm in motion estimation M. Rehan 1997
Survey on ATM switches and fault tolerance A. Amer 1997
Simulations of various inner-product processors A. Rahyhan 1997
Pseudo random number generators Z.A. Dong 1994
Specification and design of an IIR filter element M. Wedlake, W. Gaube, J. Goldstrum 1993
Systolic implementation of an IIR all-pass filter M. Fahmi 1993
HDL design of a first-order, all-pass filter section using Verilog R. Horner 1993
Hardware description language design of a first-order all pass filter section using Verilog D. Cayer, R. Leduc, R. Payne 1993
HDL design of a first-order, all-pass filter section using Verilog G. Deliyannides, C. Rory, A. Reusch 1993
Design of a digital filter processing element using the Verilog HDL D. Wiederhold, S. Khan, G. Harfman, and J. Pick 1993
Fractals and image compression E. Abdel-Raheem 1991
Adaptive filters: Theory, algorithms and applications S. Subramanian 1991
An analysis of Walsh transforms and their applications S. Radhakrishnan 1990
An examination of fractal data compression D. Caughey 1990
A study of hardware techniques to compute mathematical functions R. Byrne 1989
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