Lab location is Room ELW B326 for undergraduates. All labs are scheduled from 2:30 to 5:30. Graduates do not need to register for the labs. They can access the lab software from their research machines. In order to do the VHDL labs, one must follow the guidelines and examples explained in the Synopsys page. Guidelines for compiling and simulating VHDL code can be found in Assignments.
Home page of Dr. Gebali
Last Updated on January/26/04 By Dr. Fayez Gebali
