Selected Papers

Journal Papers

  • A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic

    Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi Journal of Low Power Electronics Vol. 5, N. 3, December 2009 (to appear)

  • History-Aware, Resource-Based Dynamic Scheduling For Heterogeneous Multi-core Processors

    Ali Jooya, Amirali Baniasadi and Morteza Analoui. IET Computers & Digital Techniques (to appear)

  • Power-aware scoreboard alternatives for multimedia processors

    Amirali Baniasadi, Babak Salamat and Kaveh Jokar Deris. Microprocessors and Microsyste\ ms Volume 33, Issue 4, June 2009, Pages 326-332

  • Power-Aware BTB for Modern Processors

    Kaveh Jokar Deris and Amirali Baniasadi. Journal of Computer and Electrical Engineering

  • Using Supplier Locality in Power-Aware Interconnects and Caches in Chip Multiprocessors

    Ehsan Atoofian and Amirali Baniasadi. Journal of Systems Architecture Vol 54, No. 5 (October 2007) pp. 507-518

  • Speculative Trivialization Point Advancing in High Performance Processors

    Ehsan Atoofian and Amirali Baniasadi. Journal of Systems Architecture, Volume 53, No. 9 (Janurary 2007), pp. 587-601

  • Exploiting Speculation Cost Prediction in Power-Aware Applications

    Ehsan Atoofian, Amirali Baniasadi and Kaveh Aasaraai. Journal of Low Power Electronics, Volume 3, No. 1 (April 2007), pp. 43-53.

  • Low-Power Perceptron Branch Predictor

    Kaveh Aasaraai and Amirali Baniasadi. Journal of Low Power Electronics, Volume 2, No. 3. (December 2006), pp. 333-341.

    Journal of Low Power Electronics
  • Improving Energy-Efficiency by Bypassing Trivial Computations

    Ehsan Atoofian and Amirali Baniasadi. IEE Proceedings Computer and Digital Techniques, Volume 153, Issue 5, pages 313-322 September 2006.

  • Energy-Aware Dynamic Resource Allocation Heuristics for Clustered Processors

    Amirali Baniasadi. IEEE Canadian Journal of Electrical and Computer Engineering, Volume 31, Number 3, pages 117-125. Summer 2006.

  • Power-Aware Branch Predictor Update

    Amirali Baniasadi. IEE Proceedings Computer and Digital Techniques, Volume 152, Issue 5, pages 585-595. September 2005.

    Conference Papers

    2010

  • System-Level Vulnerability Estimation for Cache Memories

    Alireza Haghdoost, Hossein Asadi and Amirali Baniasadi. The 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'10), December 2010.

  • HELIA: Heterogeneous Interconnect for Low Resolution Cache Access in Snoop-based Chip Multiprocessors

    Ali Shafie, Narges Shahidi and Amirali Baniasadi. The 28th International Conference on Computer Design (ICCD 2010), October 2010.

  • Using Input-to-Output Masking for System-Level Vulnerability Estimation in High-Performance Processors

    Alireza Haghdoost, Hossein Asadi and Amirali Baniasadi. The 15th CSI Symposium on Computer Architecture & Digital Systems (CADS-37), September 2010. (Best Paper)

  • Storage-Aware Value Prediction

    Mohammad Salehi and Amirali Baniasadi. The 13th Euromicro Conference on Digital System Design (DSD), September 2010.

  • Using Partial Tag Comparison in Low-Power Snoop-based Chip Multiprocessors

    Ali Shafie, Narges Shahidi and Amirali Baniasadi. The 2nd Workshop on Energy Efficient Design (WEED 2010) in conjunction with the 37th International Symposium on Computer Architecture (ISCA-37), June 2010.

  • Reconfiguring the Carry Look-Ahead Adder Using Application Behavior in Embedded Processors.

    Mohammad Hajkazemi, Alireza Haghdoost and Amirali Baniasadi. ECTI-CON 2010, May 2010.

    2009

  • Write Invalidation Analysis in Chip Multiprocessors

    Newsha Ardalan and Amirali Baniasadi. Nineteenth International Workshop on Power and Timing Modeling, Optimization and Simulation. September 2009.

  • Temperature Reduction Analysis in Sentry Tag Cache Systems

    Mostafa Farahani and Amirali Baniasadi. MEDEA 2009 Workshop MEmory performance: DEaling with Applications, systems and architecture held in conjunction with PACT 2009 Conference September 2009.

  • Application Specific Transistor Sizing for Low Power Full Adders

    Fatemeh Eslami, Amirali Baniasadi and Mostafa Farahani. The 20th IEEE International Conference on Application-specific Systems, Architectures and Processors. June 2009.

  • History-Aware, Resource-Based Dynamic Scheduling for Heterogeneous Multi-core Processors

    Ali Jooya, Amirali Baniasadi and Morteza Analoui. The 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects In conjunction with the 36th International Symposium on Computer Architecture (ISCA-36) .

    2008

  • Adaptive Read Validation in Time-Based Software Transactional Memory

    Ehsan Atoofian and Amirali Baniasadi. Proceedings of the 2nd Workshop on Highly Parallel Processing on a Chip (HPPC) in conjunction with the 14th International European Conference on Parallel and Distributed Computing (Euro-Par), August 2008.

  • Exploiting program cyclic behavior to reduce memory latency in embedded processors

    Ehsan Atoofian and Amirali Baniasadi. Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008.

    2007

  • Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters

    Daniel Vanderster, Amirali Baniasadi and Nikitas Dimopoulos. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), Seoul, Korea August 22-25, 2007.

  • A Power-Aware Alternative for the Perceptron Branch Predictor

    Kaveh Aasaraai and Amirali Baniasadi. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), Seoul, Korea August 22-25, 2007.

  • Computational and Storage Power Optimizations for the O-GEHL Branch Predictor

    Kaveh Aasaraai, Amirali Baniasadi and Ehsan Atoofian. ACM International Conference on Computing Frontiers, (CF 2007), Ischia, Italy, May 7-9, 2007.

  • Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols

    Ehsan Atoofian, Amirali Baniasadi and Kaveh Aasaraai. ACM International Conference on Computing Frontiers, (CF 2007), Ischia, Italy, May 7-9, 2007.

  • A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors

    Ehsan Atoofian and Amirali Baniasadi. Third Workshop on High-Performance, Power-Aware Computing in conjunction with IEEE International Parallel and Distributed Processing Symposium (IPDPS), 26-30 March 2007, Long Beach, CA, USA. IEEE Computer Society 2007.

    2006

  • Investigating Cache Energy and Latency Break-even Points in High Performance Processors

    Kaveh Jokar and Amirali Baniasadi. Workshop of MEmory performance: DEaling with Applications , systems and architecture (MEDEA) held in conjunction with the Fifteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2006).

  • Using Speculation Cost Predictability in Low-Power Cost-Aware Branch Prediction

    Ehsan Atoofian, Amirali Baniasadi and Farzad Khosrow-Khavar. Workshop on Complexity-Effective Design, held in conjunction with the 33rd International Symposium on Computer Architecture (ISCA-33)

  • Area-Aware Optimizations for Resource Constrained Branch Predictors Exploited in Embedded Processors

    Babak Salamat, Amirali Baniasadi and Kaveh Jokar Deris. The International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (ICSAMOS'06)

  • Reducing Execution Unit Leakage Power in Embedded Processors

    Houman Homayoun and Amirali Baniasadi. The Embedded Computer Systems: Architectures, MOdeling, and Simulation workshop (SAMOS'06)

  • SABA : a Zero Timing Overhead Power-Aware BTB for High-Performance Processors

    Kaveh Jokar Deris and Amirali Baniasadi. WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-2) held in conjunction with IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'06)

  • Using Lazy Instruction Prediction to Reduce Processor Wakeup Power Dissipation

    Houman Homayoun and Amirali Baniasadi. WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-2) held in conjunction with IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS06)

  • Branchless Cycle Prediction for Embedded Processors

    Kaveh Jokar Deris and Amirali Baniasadi. 21st ACM Symposium on Applied Computing (SAC 2006)

    2005

  • Power-Aware Scoreboard for Multimedia Processors

    Amirali Baniasadi and Babak Salamat. 7th Workshop on Media and Stream Processors (MSP-7) held in conjunction with the 38th International Symposium on Microarchitecture (MICRO 2005)

  • Area-Aware Pipeline Gating for Embedded Processors

    Babak Salamat and Amirali Baniasadi. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'05), SEP 2005.

  • Low-Power Prediction Based Data Transfer Architecture

    Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea Ismail. Custom Integrated Circuits Conference (CICC'05), SEP 2005.

  • Balancing Stalls in Clustered Processors to Improve Performance.

    Amirali Baniasadi. Second Conference on Computing Frontiers, (CF 2005), Ischia, Italy, May 4-6, 2005. ACM 2005, pp. 21-27

  • Improving Energy-Efficiency by Bypassing Trivial Computations

    Ehsan Atoofian and Amirali Baniasadi. First Workshop on High-Performance, Power-Aware Computing in conjunction with International Parallel and Distributed Processing Symposium (IPDPS'), 4-8 April 2005, Denver, CA, USA. IEEE Computer Society 2005.

    2004

  • Improving Performance by Speculating Trivializing Operands in Trivial Instructions

    Ehsan Atoofian, Amirali Baniasadi and Nikitas Dimopolous. Second Value-Prediction and Value-Based Optimization Workshop (VPW2) held in conjunction with the Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-11), OCT. 2004.

  • SEPAS: A Highly Accurate and Energy Efficient Branch Predictor.

    Amirali Baniasadi and Andreas Moshovos. Proceedings of the 2004 International Symposium on Low Power Electronics and Design, (ISLPED 2004), Newport Beach, California, USA, August 9-11, 2004. pp. 38-43

    2003

  • Power-Aware Branch Predictor Update for High-Performance Processors

    Amirali Baniasadi. International Workshop on Power And Timing Modeling, Optimization and Simulation, PATMOS-'03

  • Back-End Dynamic Resource Allocation Methods for Power-Aware High-Performance Clustered Processors

    Amirali Baniasadi. 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey. IEEE Computer Society 2003, pp. 240-247.

    2002

  • Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors

    Amirali Baniasadi and Andreas Moshovos. 20th International Conference on Computer Design (ICCD 2002), 16-18 September 2002, Freiburg, Germany, Proceedings. IEEE Computer Society 2002. pp. 420-429.

  • Asymmetric-Frequency Clustering: A Power-Aware Back-End for High-Performance Processors

    Amirali Baniasadi and Andreas Moshovos. Proceedings of the 2002 International Symposium on Low Power Electronics and Design, (ISLPED 2002), Monterey, California, USA, August 12-14, 2002. ACM 2002, pp. 255-258

    2001

  • Instruction Flow-based Front-end Throttling for Power-Aware High Performance-Processors.

    Amirali Baniasadi and Andreas Moshovos. Proceedings of the 2001 International Symposium on Low Power Electronics and Design, (ISLPED 2001), Huntington Beach, California, USA, 2001. ACM 2001, pp. 16-21

  • Slice-Processor: An Implementation of Operation-based Prediction.

    Andreas Moshovos, Dionisios N. Pnevmatikatos and Amirali Baniasadi. Proceedings of the 2001 International Conference on Supercomputing (ICS 2001), June 16-21, 2001, Sorrento, Napoli, Italy. ACM 2001, pp. 321-334.

    2000

  • Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors.

    Amirali Baniasadi and Andreas Moshovos. MICRO 33, Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 10-13 December 2000, Monterey, California, USA. pp. 337-347.

     

    Technical Reports

     

    T1.JETTY: Reducing snoop-induced power consumption in Small-Scale, Bus-Based SMP systems.

    Andreas Moshovos, Gokhan Memik,Gurav Mittal, Amirali Baniasadi and Alok Choudhary. Technical Report, CPDC, Northwestern Univ.

     

    Ph.D Thesis

    Performance and Power Optimization Techniques for High-Performance Processors

    Amirali Baniasadi